Lines Matching +full:pci +full:- +full:based

14 to change your driver to use MSI or MSI-X and some basic diagnostics to
23 The MSI capability was first specified in PCI 2.2 and was later enhanced
24 in PCI 3.0 to allow each interrupt to be masked individually.  The MSI-X
25 capability was also introduced with PCI 3.0.  It supports more interrupts
28 Devices may support both MSI and MSI-X, but only one can be enabled at
35 traditional pin-based interrupts.
37 Pin-based PCI interrupts are often shared amongst several devices.
42 When a device writes data to memory, then raises a pin-based interrupt,
44 arrived in memory (this becomes more likely with devices behind PCI-PCI
47 the interrupt.  PCI transaction ordering rules require that all the data
49 Using MSIs avoids this problem as the interrupt-generating write cannot
53 PCI devices can only support a single pin-based interrupt per function.
66 PCI devices are initialised to use pin-based interrupts.  The device
67 driver has to set up the device to use MSI or MSI-X.  Not all machines
69 will simply fail and the device will continue to use pin-based interrupts.
73 To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI
81 Most of the hard work is done for the driver in the PCI layer.  The driver
82 simply has to request that the PCI layer set up the MSI capability for this
85 To automatically use MSI or MSI-X interrupt vectors, use the following
91 which allocates up to max_vecs interrupt vectors for a PCI device.  It
94 min_vecs argument set to this limit, and the PCI core will return -ENOSPC
99 A convenient short-hand (PCI_IRQ_ALL_TYPES) is also available to ask for
113 If a device supports both MSI-X and MSI capabilities, this API will use the
114 MSI-X facilities in preference to the MSI facilities.  MSI-X supports any
118 not be able to allocate as many vectors for MSI as it could for MSI-X.  On
120 whereas MSI-X interrupts can all be targeted at different CPUs.
122 If a device supports neither MSI-X or MSI it will fall back to a single
125 The typical usage of MSI or MSI-X interrupts is to allocate as many vectors
153 the driver can specify that only MSI or MSI-X is acceptable:
161 The following old APIs to enable and disable MSI or MSI-X interrupts should
170 Additionally there are APIs to provide the number of supported MSI or MSI-X
175 pci_nr_irq_vectors() helper that handles MSI and MSI-X transparently.
181 Most device drivers have a per-device spinlock which is taken in the
182 interrupt handler.  With pin-based interrupts or a single MSI, it is not
184 not be re-entered).  If a device uses multiple interrupts, the driver
189 and acquire the lock (see Documentation/kernel-hacking/locking.rst).
191 4.5 How to tell whether MSI/MSI-X is enabled on a device
193 Using 'lspci -v' (as root) may show some devices with "MSI", "Message
194 Signalled Interrupts" or "MSI-X" capabilities.  Each of these capabilities
196 or "-" (disabled).
201 Several PCI chipsets or devices are known not to support MSIs.
202 The PCI stack provides three ways to disable MSIs:
215 quirk_disable_all_msi() function in drivers/pci/quirks.c.
217 If you have a board which has problems with MSIs, you can pass pci=nomsi
219 in your best interests to report the problem to linux-pci@vger.kernel.org
220 including a full 'lspci -v' so we can add the quirks to the kernel.
224 Some PCI bridges are not able to route MSIs between busses properly.
228 PCI configuration space (especially the Hypertransport chipsets such
235        echo 1 > /sys/bus/pci/devices/$bridge/msi_bus
237 where $bridge is the PCI address of the bridge you've enabled (eg
244 Again, please notify linux-pci@vger.kernel.org of any bridges that need
263 Then, 'lspci -t' gives the list of bridges above a device.  Reading
264 /sys/bus/pci/devices/*/msi_bus will tell you whether MSIs are enabled (1)
266 to bridges between the PCI root and the device, MSIs are disabled.