Lines Matching +full:system +full:- +full:cache +full:- +full:controller
11 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
12 counterpart. EL2 is the hypervisor level and exists only in non-secure
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36 kernel will use for volatile data storage in the system. It performs
44 -------------------------
48 The device tree blob (dtb) must be placed on an 8-byte boundary and must
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69 ------------------------
73 The decompressed kernel image contains a 64-byte header as follows:
89 - As of v3.17, all fields are little endian unless stated otherwise.
91 - code0/code1 are responsible for branching to stext.
93 - when booting through EFI, code0/code1 are initially skipped.
98 - Prior to v3.17, the endianness of text_offset was not specified. In
100 endianness of the kernel. Where image_size is non-zero image_size is
101 little-endian and must be respected. Where image_size is zero,
104 - The flags field (introduced in v3.17) is a little-endian 64-bit field
107 Bit 1-2: Kernel Page size.
108 0 - Unspecified.
109 1 - 4K
110 2 - 16K
111 3 - 64K
113 0 - 2MB aligned base should be as close as possible
116 1 - 2MB aligned base may be anywhere in physical
118 Bits 4-63: Reserved.
120 - When image_size is zero, a bootloader should attempt to keep as much
126 address anywhere in usable system RAM and called there. The region
133 placed as close as possible to the start of system RAM.
146 - Quiesce all DMA capable devices so that memory does not get
150 - Primary CPU general-purpose register settings
151 x0 = physical address of device tree blob (dtb) in system RAM.
156 - CPU mode
160 the virtualisation extensions) or non-secure EL1.
162 - Caches, MMUs
164 Instruction cache may be on or off.
166 cleaned to the PoC. In the presence of a system cache or other
168 cache maintenance by VA rather than set/way operations.
169 System caches which respect the architected cache maintenance by VA
171 System caches which do not respect architected cache maintenance by VA
174 - Architected timers
180 - Coherency
186 - System registers
187 All writable architected system registers at the exception level where
191 For systems with a GICv3 interrupt controller to be used in v3 mode:
192 - If EL3 is present:
195 - If the kernel is entered at EL1:
198 - The DT or ACPI tables must describe a GICv3 interrupt controller.
200 For systems with a GICv3 interrupt controller to be used in
202 - If EL3 is present:
204 - If the kernel is entered at EL1:
206 - The DT or ACPI tables must describe a GICv2 interrupt controller.
209 timers, coherency and system registers apply to all CPUs. All CPUs must
215 - The primary CPU must jump directly to the first instruction of the
217 an 'enable-method' property for each cpu node. The supported
218 enable-methods are described below.
223 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
225 naturally-aligned 64-bit zero-initalised memory location.
229 device tree) polling their cpu-release-addr location, which must be
231 to reduce the overhead of the busy-loop and a sev will be issued by
233 cpu-release-addr returns a non-zero value, the CPU must jump to this
234 value. The value will be written as a single 64-bit little-endian
238 - CPUs with a "psci" enable method should remain outside of
243 DEN 0022A ("Power State Coordination Interface System Software on ARM
249 - Secondary CPU general-purpose register settings