Lines Matching +full:stm32f7 +full:- +full:i2c
3 The STM32 MDMA is a general-purpose direct memory access controller capable of
7 - compatible: Should be "st,stm32h7-mdma"
8 - reg: Should contain MDMA registers location and length. This should include
9 all of the per-channel registers.
10 - interrupts: Should contain the MDMA interrupt.
11 - clocks: Should contain the input clock of the DMA instance.
12 - resets: Reference to a reset controller asserting the DMA controller.
13 - #dma-cells : Must be <5>. See DMA client paragraph for more details.
16 - dma-channels: Number of DMA channels supported by the controller.
17 - dma-requests: Number of DMA request signals supported by the controller.
18 - st,ahb-addr-masks: Array of u32 mask to list memory devices addressed via
24 compatible = "st,stm32h7-mdma";
29 #dma-cells = <5>;
30 dma-channels = <16>;
31 dma-requests = <32>;
32 st,ahb-addr-masks = <0x20000000>, <0x00000000>;
38 described in the dma.txt file, using a five-cell specifier for each channel:
48 -bit 0-1: Source increment mode
52 -bit 2-3: Destination increment mode
58 -bit 8-9: Source increment offset size
60 0x01: half-word (16bit)
62 0x11: double-word (64bit)
63 -bit 10-11: Destination increment offset size
65 0x01: half-word (16bit)
67 0x11: double-word (64bit)
68 -bit 25-18: The number of bytes to be transferred in a single transfer
70 -bit 29:28: Trigger Mode
82 i2c4: i2c@5c002000 {
83 compatible = "st,stm32f7-i2c";
88 #address-cells = <1>;
89 #size-cells = <0>;
92 dma-names = "rx", "tx";