Lines Matching +full:resistance +full:- +full:temp +full:- +full:table
7 Addresses scanned: none, address read from Super-I/O config space
20 -----------------
23 configuration for channels 1-5.
24 Legal values are in the range of 0-31. Bit 0 maps to
40 -----------
42 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
45 implements 5 universal input channels (UCH1-5) that can be individually
53 connected to the PWM outputs of the VT1211 :-().
55 The following table shows the relationship between the vt1211 inputs and the
58 Sensor Voltage Mode Temp Mode Default Use (from the datasheet)
59 ------ ------------ --------- --------------------------------
71 ------------------
73 Voltages are sampled by an 8-bit ADC with a LSB of ~10mV. The supported input
82 implementation :-) You will have to find documentation for your own
87 -----------------------------------------------
89 VccP --- --- 1.0 1400 mV (1)
104 ----------------------
116 temp1 and temp3-temp7, scaling depends on the board implementation and needs
119 Temp1 is an Intel-type thermal diode which requires the following formula to
122 compute temp1 (@-Offset)/Gain, (@*Gain)+Offset
128 ---------- ------ ----
132 VIA C3 Ezra-T 73.869 0.9528
138 Temp3-temp7 support NTC thermistors. For these channels, the driver returns
139 the voltages as seen at the individual pins of UCH1-UCH5. The voltage at the
148 Rth = Ro * exp(B * (1 / T - 1 / To)) (To is 298.15K (25C) and Ro is the
149 nominal resistance at 25C)
154 compute tempx 1 / (1 / 298.15 - (` (2200 / @ - 1)) / 3435) - 273.15,
155 2200 / (1 + (^ (3435 / 298.15 - 3435 / (273.15 + @))))
159 -----------------
162 fans. Writing a 2 to any of the two pwm[1-2]_enable sysfs nodes will put the
167 Each PWM has 4 associated distinct output duty-cycles: full, high, low and
168 off. Full and off are internally hard-wired to 255 (100%) and 0 (0%),
170 pwm[1-2]_auto_point[2-3]_pwm. Each PWM output can be associated with a
171 different thermal input but - and here's the weird part - only one set of
172 thermal thresholds exist that controls both PWMs output duty-cycles. The
173 thermal thresholds are accessible via pwm[1-2]_auto_point[1-4]_temp. Note
176 the first set pwm1_auto_point[1-4]_temp is writable, the second set is
177 read-only).
179 PWM Auto Point PWM Output Duty-Cycle
180 ------------------------------------------------
181 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
182 pwm[1-2]_auto_point3_pwm high speed duty-cycle
183 pwm[1-2]_auto_point2_pwm low speed duty-cycle
184 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
186 Temp Auto Point Thermal Threshold
187 ---------------------------------------------
188 pwm[1-2]_auto_point4_temp full speed temp
189 pwm[1-2]_auto_point3_temp high speed temp
190 pwm[1-2]_auto_point2_temp low speed temp
191 pwm[1-2]_auto_point1_temp off temp
194 PWM output duty-cycle based on the input temperature:
196 Thermal Threshold Output Duty-Cycle
197 (Rising Temp) (Falling Temp)
198 ----------------------------------------------------------
199 full speed duty-cycle full speed duty-cycle
200 full speed temp
201 high speed duty-cycle full speed duty-cycle
202 high speed temp
203 low speed duty-cycle high speed duty-cycle
204 low speed temp
205 off duty-cycle low speed duty-cycle
206 off temp