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4 The following is a summary of the SMBus protocol. It applies to
10 which is a subset from the I2C protocol. Fortunately, many devices use
13 If you write a driver for some I2C device, please try to use the SMBus
20 Below is a list of SMBus protocol operations, and the functions executing
22 don't match these function names. For some of the operations which pass a
24 a different protocol operation entirely.
26 Each transaction type corresponds to a functionality flag. Before calling a
27 transaction function, a device driver should always check (just once) for
39 A, NA (1 bit) : Accept and reverse accept bit.
41 get a 10 bit I2C address.
42 Comm (8 bits): Command byte, a data byte which often selects a register on
44 Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
46 Count (8 bits): A data byte containing the length of a block operation.
54 This sends a single bit to the device, at the place of the Rd/Wr bit.
56 A Addr Rd/Wr [A] P
64 This reads a single byte from a device, without specifying a device
66 others, it is a shorthand if you want to read the same register as in
69 S Addr Rd [A] [Data] NA P
77 This operation is the reverse of Receive Byte: it sends a single byte
78 to a device. See Receive Byte for more information.
80 S Addr Wr [A] Data [A] P
88 This reads a single byte from a device, from a designated register.
91 S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
99 This operation is very like Read Byte; again, data is read from a
100 device, from a designated register that is specified through the Comm
101 byte. But this time, the data is a complete word (16 bits).
103 S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
115 This writes a single byte to a device, to a designated register. The
119 S Addr Wr [A] Comm [A] Data [A] P
128 of data is written to a device, to the designated register that is
131 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
143 This command selects a device register (through the Comm byte), sends
146 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
147 S Addr Rd [A] [DataLow] A [DataHigh] NA P
155 This command reads a block of up to 32 bytes from a device, from a
159 S Addr Wr [A] Comm [A]
160 S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
169 a device, to a designated register that is specified through the
172 S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
183 This command selects a device register (through the Comm byte), sends
186 S Addr Wr [A] Comm [A] Count [A] Data [A] ...
187 S Addr Rd [A] [Count] A [Data] ... A P
195 This command is sent from a SMBus device acting as a master to the
196 SMBus host acting as a slave.
200 [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
205 * I2C bus drivers trigger SMBus Host Notify by a call to
208 client->irq assigned to a Host Notify IRQ if noone else specified an other.
218 PEC adds a CRC-8 error-checking byte to transfers using it, immediately
226 the specification. It is a higher-layer protocol which uses the
239 The SMBus alert protocol allows several SMBus slave devices to share a
258 but the SMBus layer places a limit of 32 bytes.
264 This command reads a block of bytes from a device, from a
267 S Addr Wr [A] Comm [A]
268 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
277 a device, to a designated register that is specified through the
281 S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P