Lines Matching full:debug
1 Coresight CPU Debug Module
10 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
11 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
12 debug module and it is mainly used for two modes: self-hosted debug and
13 external debug. Usually the external debug mode is well known as the external
15 explore debugging method which rely on self-hosted debug mode, this document
18 The debug module provides sample-based profiling extension, which can be used
20 every CPU has one dedicated debug module to be connected. Based on self-hosted
21 debug mechanism, Linux kernel can access these related registers from mmio
35 - At the time this documentation was written, the debug driver mainly relies on
68 Before accessing debug registers, we should ensure the clock and power domain
70 Debug registers', the debug registers are spread into two domains: the debug
78 | Debug |**| CPU |
85 For debug domain, the user uses DT binding "clocks" and "power-domains" to
86 specify the corresponding clock source and power supply for the debug logic.
88 debug power domain.
91 schemes and finally this heavily impacts external debug module. So we can
99 powered on properly during the period when access debug related registers;
102 are powered down - including the parts of the debug registers that should
103 remain powered in the debug power domain. The bits in EDPRCR are not
104 respected in these cases, so these designs do not support debug over
105 power down in the way that the CoreSight / Debug designers anticipated.
109 In this case, accessing to the debug registers while they are not powered
118 See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
129 # insmod coresight_cpu_debug.ko debug=1
135 To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable:
136 # echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
138 To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable:
139 # echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable
142 platform which has idle states to power off debug logic and the power
145 ensure the accessing to debug logic.
177 ARM external debug module:
178 coresight-cpu-debug 850000.debug: CPU[0]:
179 coresight-cpu-debug 850000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
180 coresight-cpu-debug 850000.debug: EDPCSR: handle_IPI+0x174/0x1d8
181 coresight-cpu-debug 850000.debug: EDCIDSR: 00000000
182 coresight-cpu-debug 850000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID…
183 coresight-cpu-debug 852000.debug: CPU[1]:
184 coresight-cpu-debug 852000.debug: EDPRSR: 00000001 (Power:On DLK:Unlock)
185 coresight-cpu-debug 852000.debug: EDPCSR: debug_notifier_call+0x23c/0x358
186 coresight-cpu-debug 852000.debug: EDCIDSR: 00000000
187 coresight-cpu-debug 852000.debug: EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID…