Lines Matching +full:memory +full:- +full:to +full:- +full:memory
4 Heterogeneous Memory Management (HMM)
7 Provide infrastructure and helpers to integrate non-conventional memory (device
8 memory like GPU on board memory) into regular kernel path, with the cornerstone
9 of this being specialized struct page for such memory (see sections 5 to 7 of
12 HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
13 allowing a device to transparently access program address coherently with
15 for the device. This is becoming mandatory to simplify the use of advanced
16 heterogeneous computing where GPU, DSP, or FPGA are used to perform various
20 related to using device specific memory allocators. In the second section, I
21 expose the hardware limitations that are inherent to many platforms. The third
23 CPU page-table mirroring works and the purpose of HMM in this context. The
24 fifth section deals with how device memory is represented inside the kernel.
25 Finally, the last section presents a new migration helper that allows lever-
30 Problems of using a device specific memory allocator
33 Devices with a large amount of on board memory (several gigabytes) like GPUs
34 have historically managed their memory through dedicated driver specific APIs.
35 This creates a disconnect between memory allocated and managed by a device
36 driver and regular application memory (private anonymous, shared memory, or
37 regular file backed memory). From here on I will refer to this aspect as split
38 address space. I use shared address space to refer to the opposite situation:
39 i.e., one in which any application memory region can be used by a device
42 Split address space happens because device can only access memory allocated
43 through device specific API. This implies that all memory objects in a program
47 Concretely this means that code that wants to leverage devices like GPUs needs
48 to copy object between generically allocated memory (malloc, mmap private, mmap
49 share) and memory allocated through the device driver API (this still ends up
52 For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
53 complex data sets (list, tree, ...) are hard to get right. Duplicating a
54 complex data set needs to re-map all the pointer relations between each of its
55 elements. This is error prone and program gets harder to debug because of the
60 might have to duplicate its input data set using the device specific memory
62 various memory copies.
64 Duplicating each library API to accept as input or output memory allocated by
65 each device specific allocator is not a viable option. It would lead to a
69 other languages too) it is now possible for the compiler to leverage GPUs and
71 are only do-able with a shared address space. It is also more reasonable to use
75 I/O bus, device memory characteristics
78 I/O buses cripple shared address spaces due to a few limitations. Most I/O
79 buses only allow basic memory access from device to main memory; even cache
80 coherency is often optional. Access to device memory from CPU is even more
83 If we only consider the PCIE bus, then a device can access main memory (often
85 a limited set of atomic operations from device on main memory. This is worse
87 memory and cannot perform atomic operations on it. Thus device memory cannot
88 be considered the same as regular memory from the kernel point of view.
91 and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
92 The final limitation is latency. Access to main memory from the device has an
93 order of magnitude higher latency than when the device accesses its own memory.
95 Some platforms are developing new I/O buses or additions/modifications to PCIE
96 to address some of these limitations (OpenCAPI, CCIX). They mainly allow two-
99 some major architectures are left without hardware solutions to these problems.
101 So for shared address space to make sense, not only must we allow devices to
102 access any memory but we must also permit any memory to be migrated to device
103 memory while device is using it (blocking CPU access while it happens).
109 HMM intends to provide two main features. First one is to share the address
111 address points to the same physical memory for any valid main memory address in
114 To achieve this, HMM offers a set of helpers to populate the device page table
116 not as easy as CPU page table updates. To update the device page table, you must
117 allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
118 specific commands in it to perform the update (unmap, cache invalidations, and
120 why HMM provides helpers to factor out everything that can be while leaving the
121 hardware specific details to the device driver.
123 The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
124 allows allocating a struct page for each page of the device memory. Those pages
126 main memory to device memory using existing migration mechanisms and everything
127 looks like a page is swapped out to disk from the CPU point of view. Using a
128 struct page gives the easiest and cleanest integration with existing mm mech-
129 anisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
130 memory for the device memory and second to perform migration. Policy decisions
131 of what and when to migrate things is left to the device driver.
133 Note that any CPU access to a device page triggers a page fault and a migration
134 back to main memory. For example, when a page backing a given CPU address A is
135 migrated from a main memory page to a device page, then any CPU access to
136 address A triggers a page fault and initiates a migration back to main memory.
138 With these two features, HMM not only allows a device to mirror process address
139 space and keeping both CPU and device page table synchronized, but also lever-
140 ages device memory by migrating the part of the data set that is actively being
147 Address space mirroring's main objective is to allow duplication of a range of
149 device driver that wants to mirror a process address space must start with the
158 The locked variant is to be used when the driver is already holding mmap_sem
160 to propagate CPU page tables::
163 /* sync_cpu_device_pagetables() - synchronize page tables
165 * @mirror: pointer to struct hmm_mirror
166 * @update_type: type of update that occurred to the CPU page table
167 * @start: virtual start address of the range to update
168 * @end: virtual end address of the range to update
172 * in response to this callback. The update argument tells what action
173 * to perform.
185 The device driver must perform the update action to the range (mark range
189 When the device driver wants to populate a range of virtual addresses, it can
206 entries and will not trigger a page fault on missing or non-present entries.
207 The second one does trigger a page fault on missing or read-only entry if the
212 entry in that array corresponds to an address in the virtual range. HMM
213 provides a set of flags to help the driver identify special CPU page table
217 respect in order to keep things properly synchronized. The usage pattern is::
227 take_lock(driver->update);
229 release_lock(driver->update);
233 // Use pfns array content to update device page table
235 release_lock(driver->update);
239 The driver->update lock is the same lock that the driver takes inside its
240 update() callback. That lock must be held before hmm_vma_range_done() to avoid
244 simpler API and also to be able to perform optimizations latter on like doing
245 concurrent device updates in multi-devices scenario.
248 are done (by CPU write to the page table and TLB flushes) and how devices
249 update their own page table. Device updates are a multi-step process. First,
250 appropriate commands are written to a buffer, then this buffer is scheduled for
253 buffer can happen concurrently for multiple devices. Waiting for each device to
258 Represent and manage device memory from core kernel point of view
261 Several different designs were tried to support device memory. First one used
262 a device specific data structure to keep information about migrated memory and
263 HMM hooked itself in various places of mm code to handle any access to
264 addresses that were backed by device memory. It turns out that this ended up
266 paths to be updated to understand this new kind of memory.
268 Most kernel code paths never try to access the memory behind a page
269 but only care about struct page contents. Because of this, HMM switched to
270 directly using struct page for device memory which left most kernel code paths
271 unaware of the difference. We only need to make sure that no one ever tries to
274 HMM provides a set of helpers to register and hotplug device memory as a new
296 The second callback happens whenever the CPU tries to access a device page
297 which it cannot do. This second callback must trigger a migration back to
298 system memory.
301 Migration to and from device memory
304 Because the CPU cannot access device memory, migration must use the device DMA
305 engine to perform copy from and to device memory. For this we need a new
324 controls destination memory allocation and copy operation. Second one is there
325 to allow the device driver to perform cleanup operations after migration::
342 It is important to stress that these migration helpers allow for holes in the
347 The alloc_and_copy() might decide to not migrate all pages in the
349 has to leave the corresponding dst entry empty.
352 various reasons (failure to freeze reference, or update page cache, ...). If
354 migrated. Note those pages were still copied to a new page and thus we wasted
356 willing to pay to keep all the code simpler.
359 Memory cgroup (memcg) and rss accounting
362 For now device memory is accounted as any regular page in rss counters (either
364 file backed page or shmem if device page is used for shared memory). This is a
365 deliberate choice to keep existing applications, that might start using device
366 memory without knowing about it, running unimpacted.
369 device memory and not a lot of regular system memory and thus not freeing much
370 system memory. We want to gather more real world experience on how applications
371 and system react under memory pressure in the presence of device memory before
372 deciding to account device memory differently.
375 Same decision was made for memory cgroup. Device memory pages are accounted
376 against same memory cgroup a regular page would be accounted to. This does
377 simplify migration to and from device memory. This also means that migration
378 back from device memory to regular memory cannot fail because it would
379 go above memory cgroup limit. We might revisit this choice latter on once we
380 get more experience in how device memory is used and its impact on memory
384 Note that device memory can never be pinned by device driver nor through GUP
385 and thus such memory is always free upon process exit. Or when last reference
386 is dropped in case of shared memory or file backed memory.