Lines Matching +full:cpu +full:- +full:intc
2 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
10 * Device tree for AXC001 770D/EM6/AS221 CPU card
11 * Note that this file only supports the 770D CPU
18 #address-cells = <2>;
19 #size-cells = <2>;
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <1>;
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <750000000>;
34 core_intc: arc700-intc@cpu {
35 compatible = "snps,arc700-intc";
36 interrupt-controller;
37 #interrupt-cells = <1>;
41 * this GPIO block ORs all interrupts on CPU card (creg,..)
42 * to uplink only 1 IRQ to ARC core intc
44 dw-apb-gpio@0x2000 {
45 compatible = "snps,dw-apb-gpio";
47 #address-cells = <1>;
48 #size-cells = <0>;
50 ictl_intc: gpio-controller@0 {
51 compatible = "snps,dw-apb-gpio-port";
52 gpio-controller;
53 #gpio-cells = <2>;
54 snps,nr-gpios = <30>;
56 interrupt-controller;
57 #interrupt-cells = <2>;
58 interrupt-parent = <&core_intc>;
63 debug_uart: dw-apb-uart@0x5000 {
64 compatible = "snps,dw-apb-uart";
66 clock-frequency = <33333000>;
67 interrupt-parent = <&ictl_intc>;
70 reg-shift = <2>;
71 reg-io-width = <4>;
75 compatible = "snps,arc700-pct";
80 * This INTC is actually connected to DW APB GPIO
81 * which acts as a wire between MB INTC and CPU INTC.
82 * GPIO INTC is configured in platform init code
83 * and here we mimic direct connection from MB INTC to
84 * CPU INTC, thus we set "interrupts = <7>" instead of
87 * This intc actually resides on MB, but we move it here to
89 * this intc to cpu intc are different for axs101 and axs103
91 mb_intc: dw-apb-ictl@0xe0012000 {
92 #interrupt-cells = <1>;
93 compatible = "snps,dw-apb-ictl";
95 interrupt-controller;
96 interrupt-parent = <&core_intc>;
103 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
106 reserved-memory {
107 #address-cells = <2>;
108 #size-cells = <2>;
113 * no strict requirement for a frame-buffer to be in any
118 compatible = "shared-dma-pool";
120 no-map;