Lines Matching +full:re +full:- +full:configured

2  * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
22  * -Platform independent, needed for each CPU (not foldable into init_IRQ)
23  * -Called very early (start_kernel -> setup_arch -> setup_processor)
26  * -Optionally, setup the High priority Interrupts as Level 2 IRQs
36 	 * Write to register, even if no LV2 IRQs configured to reset it  in arc_init_IRQ()
42 		pr_info("Level-2 interrupts bitset %x\n", level_mask);  in arc_init_IRQ()
58  * ARC700 core includes a simple on-chip intc supporting
59  * -per IRQ enable/disable
60  * -2 levels of interrupts (high/low)
61  * -all interrupts being level triggered
63  * To reduce platform code, we assume all IRQs directly hooked-up into intc.
64  * Platforms with external intc, hence cascaded IRQs, are free to over-ride
73 	ienb &= ~(1 << data->hwirq);  in arc_irq_mask()
82 	ienb |= (1 << data->hwirq);  in arc_irq_unmask()
87 	.name           = "ARC In-core Intc",
133 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
136  * arch_local_irq_enable - Enable interrupts.
138  * 1. Explicitly called to re-enable interrupts
144  * -If called from hard-ISR, it must not invert interrupt priorities
146  *    Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
147  *    Here local_irq_enable( ) shd not re-enable lower priority interrupts
148  * -If called from soft-ISR, it must re-enable all interrupts
152  *    still we must re-enable both L1 and L2 IRQs
155  *     here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
156  *     over-written (this is deficiency in ARC700 Interrupt mechanism)