Lines Matching +full:6 +full:- +full:axis
2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
49 compatible = "axis,artpec6";
50 interrupt-parent = <&intc>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
60 next-level-cache = <&pl310>;
65 compatible = "arm,cortex-a9";
67 next-level-cache = <&pl310>;
72 compatible = "axis,artpec6-syscon", "syscon";
77 compatible = "arm,psci-0.2", "arm,psci";
85 compatible = "arm,cortex-a9-scu";
91 #clock-cells = <0>;
92 compatible = "fixed-clock";
93 clock-frequency = <50000000>;
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-frequency = <125000000>;
103 #clock-cells = <1>;
104 compatible = "axis,artpec6-clkctrl";
107 clock-names = "sys_refclk";
111 compatible = "arm,cortex-a9-global-timer";
118 compatible = "arm,cortex-a9-twd-timer";
125 intc: interrupt-controller@faf01000 {
126 interrupt-controller;
127 compatible = "arm,cortex-a9-gic";
128 #interrupt-cells = <3>;
132 pl310: cache-controller@faf10000 {
133 compatible = "arm,pl310-cache";
134 cache-unified;
135 cache-level = <2>;
138 arm,data-latency = <1 1 1>;
139 arm,tag-latency = <1 1 1>;
140 arm,filter-ranges = <0x0 0x80000000>;
141 arm,double-linefill = <1>;
142 arm,double-linefill-incr = <0>;
143 arm,double-linefill-wrap = <0>;
144 prefetch-data = <1>;
145 prefetch-instr = <1>;
146 arm,prefetch-offset = <0>;
147 arm,prefetch-drop = <1>;
151 compatible = "arm,cortex-a9-pmu";
154 interrupt-affinity = <&cpu0>, <&cpu1>;
162 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
166 reg-names = "dbi", "phy", "config";
167 #address-cells = <3>;
168 #size-cells = <2>;
172 /* non-prefetchable memory */
174 num-lanes = <2>;
175 bus-range = <0x00 0xff>;
177 interrupt-names = "msi";
178 #interrupt-cells = <1>;
179 interrupt-map-mask = <0 0 0 0x7>;
180 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
184 axis,syscon-pcie = <&syscon>;
189 compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
194 reg-names = "dbi", "dbi2", "phy", "addr_space";
195 num-ib-windows = <6>;
196 num-ob-windows = <2>;
197 num-lanes = <2>;
198 axis,syscon-pcie = <&syscon>;
203 compatible = "axis,artpec6-pinctrl";
209 bias-pull-up;
214 bias-pull-up;
219 bias-pull-up;
224 bias-pull-up;
229 compatible = "simple-bus";
230 #address-cells = <0x1>;
231 #size-cells = <0x1>;
233 dma-ranges;
236 compatible = "axis,artpec6-crypto";
253 interrupt-names = "error",
259 #dma-cells = <2>;
260 dma-channels = <8>;
261 dma-requests = <8>;
275 interrupt-names = "error",
281 #dma-cells = <2>;
282 dma-channels = <8>;
283 dma-requests = <8>;
287 clock-names = "stmmaceth", "ptp_ref";
290 compatible = "snps,dwmac-4.10a", "snps,dwmac";
293 interrupt-names = "macirq", "eth_lpi";
296 snps,axi-config = <&stmmac_axi_setup>;
297 snps,mtl-rx-config = <&mtl_rx_setup>;
298 snps,mtl-tx-config = <&mtl_tx_setup>;
307 stmmac_axi_setup: stmmac-axi-config {
318 mtl_rx_setup: rx-queues-config {
319 snps,rx-queues-to-use = <1>;
323 mtl_tx_setup: tx-queues-config {
324 snps,tx-queues-to-use = <2>;
336 clock-names = "uart_clk", "apb_pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_uart0>;
341 dma-names = "rx", "tx";
350 clock-names = "uart_clk", "apb_pclk";
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_uart1>;
353 dmas = <&dma0 6 (NBPF_SLAVE_RQ_HIGH | NBPF_SLAVE_RQ_LEVEL)>,
355 dma-names = "rx", "tx";
364 clock-names = "uart_clk", "apb_pclk";
365 pinctrl-names = "default";
366 pinctrl-0 = <&pinctrl_uart2>;
369 dma-names = "rx", "tx";
378 clock-names = "uart_clk", "apb_pclk";
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_uart3>;
383 dma-names = "rx", "tx";