Lines Matching +full:clock +full:- +full:controller
4 * Copyright (C) 2012-2013 Hisilicon Ltd.
5 * Copyright (C) 2012-2013 Linaro Ltd.
14 #include <dt-bindings/clock/hi3620-clock.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <26000000>;
32 clock-output-names = "apb_pclk";
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "hisilicon,hi3620-smp";
42 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
48 compatible = "arm,cortex-a9";
51 next-level-cache = <&L2>;
55 compatible = "arm,cortex-a9";
58 next-level-cache = <&L2>;
62 compatible = "arm,cortex-a9";
65 next-level-cache = <&L2>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "simple-bus";
74 interrupt-parent = <&gic>;
77 L2: l2-cache {
78 compatible = "arm,pl310-cache";
81 cache-unified;
82 cache-level = <2>;
85 gic: interrupt-controller@1000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 #address-cells = <0>;
89 interrupt-controller;
94 sysctrl: system-controller@802000 {
96 #address-cells = <1>;
97 #size-cells = <1>;
101 smp-offset = <0x31c>;
102 resume-offset = <0x308>;
103 reboot-offset = <0x4>;
105 clock: clock@0 { label
106 compatible = "hisilicon,hi3620-clock";
108 #clock-cells = <1>;
117 clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
118 clock-names = "apb_pclk";
127 clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
128 clock-names = "apb_pclk";
137 clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
138 clock-names = "apb_pclk";
147 clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
148 clock-names = "apb_pclk";
157 clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
158 clock-names = "apb_pclk";
163 compatible = "arm,cortex-a9-twd-timer";
172 clocks = <&clock HI3620_UARTCLK0>;
173 clock-names = "apb_pclk";
181 clocks = <&clock HI3620_UARTCLK1>;
182 clock-names = "apb_pclk";
190 clocks = <&clock HI3620_UARTCLK2>;
191 clock-names = "apb_pclk";
199 clocks = <&clock HI3620_UARTCLK3>;
200 clock-names = "apb_pclk";
208 clocks = <&clock HI3620_UARTCLK4>;
209 clock-names = "apb_pclk";
217 gpio-controller;
218 #gpio-cells = <2>;
219 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 clocks = <&clock HI3620_GPIOCLK0>;
224 clock-names = "apb_pclk";
231 gpio-controller;
232 #gpio-cells = <2>;
233 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 clocks = <&clock HI3620_GPIOCLK1>;
239 clock-names = "apb_pclk";
246 gpio-controller;
247 #gpio-cells = <2>;
248 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 clocks = <&clock HI3620_GPIOCLK2>;
254 clock-names = "apb_pclk";
261 gpio-controller;
262 #gpio-cells = <2>;
263 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
266 interrupt-controller;
267 #interrupt-cells = <2>;
268 clocks = <&clock HI3620_GPIOCLK3>;
269 clock-names = "apb_pclk";
276 gpio-controller;
277 #gpio-cells = <2>;
278 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 clocks = <&clock HI3620_GPIOCLK4>;
284 clock-names = "apb_pclk";
291 gpio-controller;
292 #gpio-cells = <2>;
293 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 clocks = <&clock HI3620_GPIOCLK5>;
299 clock-names = "apb_pclk";
306 gpio-controller;
307 #gpio-cells = <2>;
308 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 clocks = <&clock HI3620_GPIOCLK6>;
314 clock-names = "apb_pclk";
321 gpio-controller;
322 #gpio-cells = <2>;
323 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
326 interrupt-controller;
327 #interrupt-cells = <2>;
328 clocks = <&clock HI3620_GPIOCLK7>;
329 clock-names = "apb_pclk";
336 gpio-controller;
337 #gpio-cells = <2>;
338 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
341 interrupt-controller;
342 #interrupt-cells = <2>;
343 clocks = <&clock HI3620_GPIOCLK8>;
344 clock-names = "apb_pclk";
351 gpio-controller;
352 #gpio-cells = <2>;
353 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 clocks = <&clock HI3620_GPIOCLK9>;
359 clock-names = "apb_pclk";
366 gpio-controller;
367 #gpio-cells = <2>;
368 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
370 interrupt-controller;
371 #interrupt-cells = <2>;
372 clocks = <&clock HI3620_GPIOCLK10>;
373 clock-names = "apb_pclk";
380 gpio-controller;
381 #gpio-cells = <2>;
382 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
385 interrupt-controller;
386 #interrupt-cells = <2>;
387 clocks = <&clock HI3620_GPIOCLK11>;
388 clock-names = "apb_pclk";
395 gpio-controller;
396 #gpio-cells = <2>;
397 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 clocks = <&clock HI3620_GPIOCLK12>;
403 clock-names = "apb_pclk";
410 gpio-controller;
411 #gpio-cells = <2>;
412 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
415 interrupt-controller;
416 #interrupt-cells = <2>;
417 clocks = <&clock HI3620_GPIOCLK13>;
418 clock-names = "apb_pclk";
425 gpio-controller;
426 #gpio-cells = <2>;
427 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
430 interrupt-controller;
431 #interrupt-cells = <2>;
432 clocks = <&clock HI3620_GPIOCLK14>;
433 clock-names = "apb_pclk";
440 gpio-controller;
441 #gpio-cells = <2>;
442 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 clocks = <&clock HI3620_GPIOCLK15>;
448 clock-names = "apb_pclk";
455 gpio-controller;
456 #gpio-cells = <2>;
457 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 clocks = <&clock HI3620_GPIOCLK16>;
463 clock-names = "apb_pclk";
470 gpio-controller;
471 #gpio-cells = <2>;
472 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
475 interrupt-controller;
476 #interrupt-cells = <2>;
477 clocks = <&clock HI3620_GPIOCLK17>;
478 clock-names = "apb_pclk";
485 gpio-controller;
486 #gpio-cells = <2>;
487 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 clocks = <&clock HI3620_GPIOCLK18>;
493 clock-names = "apb_pclk";
500 gpio-controller;
501 #gpio-cells = <2>;
502 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 clocks = <&clock HI3620_GPIOCLK19>;
507 clock-names = "apb_pclk";
514 gpio-controller;
515 #gpio-cells = <2>;
516 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 clocks = <&clock HI3620_GPIOCLK20>;
521 clock-names = "apb_pclk";
528 gpio-controller;
529 #gpio-cells = <2>;
530 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
531 interrupt-controller;
532 #interrupt-cells = <2>;
533 clocks = <&clock HI3620_GPIOCLK21>;
534 clock-names = "apb_pclk";
538 compatible = "pinctrl-single";
540 #address-cells = <1>;
541 #size-cells = <1>;
542 #pinctrl-cells = <1>;
543 #gpio-range-cells = <3>;
546 pinctrl-single,register-width = <32>;
547 pinctrl-single,function-mask = <7>;
549 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
554 range: gpio-range {
555 #pinctrl-single,gpio-range-cells = <3>;
560 compatible = "pinconf-single";
562 #address-cells = <1>;
563 #size-cells = <1>;
564 #pinctrl-cells = <1>;
567 pinctrl-single,register-width = <32>;