Lines Matching +full:ddr +full:- +full:pmu
2 * Copyright 2011-2012 Calxeda, Inc.
17 /dts-v1/;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 clock-ranges;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a9";
37 next-level-cache = <&L2>;
39 clock-names = "cpu";
40 operating-points = <
49 clock-latency = <100000>;
53 compatible = "arm,cortex-a9";
56 next-level-cache = <&L2>;
58 clock-names = "cpu";
59 operating-points = <
68 clock-latency = <100000>;
72 compatible = "arm,cortex-a9";
75 next-level-cache = <&L2>;
77 clock-names = "cpu";
78 operating-points = <
87 clock-latency = <100000>;
91 compatible = "arm,cortex-a9";
94 next-level-cache = <&L2>;
96 clock-names = "cpu";
97 operating-points = <
106 clock-latency = <100000>;
119 memory-controller@fff00000 {
120 compatible = "calxeda,hb-ddr-ctrl";
126 compatible = "arm,cortex-a9-twd-timer";
133 compatible = "arm,cortex-a9-twd-wdt";
139 intc: interrupt-controller@fff11000 {
140 compatible = "arm,cortex-a9-gic";
141 #interrupt-cells = <3>;
142 #size-cells = <0>;
143 #address-cells = <1>;
144 interrupt-controller;
149 L2: l2-cache {
150 compatible = "arm,pl310-cache";
153 cache-unified;
154 cache-level = <2>;
157 pmu {
158 compatible = "arm,cortex-a9-pmu";
164 compatible = "calxeda,hb-sregs-l2-ecc";
172 /include/ "ecx-common.dtsi"