Lines Matching +full:gcc +full:- +full:msm8960
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 interrupt-parent = <&intc>;
17 reserved-memory {
18 #address-cells = <1>;
19 #size-cells = <1>;
24 no-map;
29 no-map;
34 #address-cells = <1>;
35 #size-cells = <0>;
39 enable-method = "qcom,kpss-acc-v1";
42 next-level-cache = <&L2>;
45 cpu-idle-states = <&CPU_SPC>;
50 enable-method = "qcom,kpss-acc-v1";
53 next-level-cache = <&L2>;
56 cpu-idle-states = <&CPU_SPC>;
61 enable-method = "qcom,kpss-acc-v1";
64 next-level-cache = <&L2>;
67 cpu-idle-states = <&CPU_SPC>;
72 enable-method = "qcom,kpss-acc-v1";
75 next-level-cache = <&L2>;
78 cpu-idle-states = <&CPU_SPC>;
81 L2: l2-cache {
83 cache-level = <2>;
86 idle-states {
88 compatible = "qcom,idle-state-spc",
89 "arm,idle-state";
90 entry-latency-us = <400>;
91 exit-latency-us = <900>;
92 min-residency-us = <3000>;
97 thermal-zones {
98 cpu-thermal0 {
99 polling-delay-passive = <250>;
100 polling-delay = <1000>;
102 thermal-sensors = <&gcc 7>;
119 cpu-thermal1 {
120 polling-delay-passive = <250>;
121 polling-delay = <1000>;
123 thermal-sensors = <&gcc 8>;
140 cpu-thermal2 {
141 polling-delay-passive = <250>;
142 polling-delay = <1000>;
144 thermal-sensors = <&gcc 9>;
161 cpu-thermal3 {
162 polling-delay-passive = <250>;
163 polling-delay = <1000>;
165 thermal-sensors = <&gcc 10>;
183 cpu-pmu {
184 compatible = "qcom,krait-pmu";
190 compatible = "fixed-clock";
191 #clock-cells = <0>;
192 clock-frequency = <19200000>;
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <27000000>;
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <32768>;
209 compatible = "qcom,sfpb-mutex";
211 #hwlock-cells = <1>;
216 memory-region = <&smem_region>;
228 qcom,smd-edge = <0>;
237 qcom,smd-edge = <1>;
246 qcom,smd-edge = <3>;
255 qcom,smd-edge = <6>;
264 #address-cells = <1>;
265 #size-cells = <0>;
267 qcom,ipc-1 = <&l2cc 8 4>;
268 qcom,ipc-2 = <&l2cc 8 14>;
269 qcom,ipc-3 = <&l2cc 8 23>;
270 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
274 #qcom,smem-state-cells = <1>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
289 interrupt-controller;
290 #interrupt-cells = <2>;
297 interrupt-controller;
298 #interrupt-cells = <2>;
305 interrupt-controller;
306 #interrupt-cells = <2>;
312 compatible = "qcom,scm-apq8064";
315 clock-names = "core";
322 * That is why the ADC is referred to as "HKADC" - HouseKeeping
325 iio-hwmon {
326 compatible = "iio-hwmon";
327 io-channels = <&xoadc 0x00 0x01>, /* Battery */
337 #address-cells = <1>;
338 #size-cells = <1>;
340 compatible = "simple-bus";
343 compatible = "qcom,apq8064-pinctrl";
346 gpio-controller;
347 #gpio-cells = <2>;
348 interrupt-controller;
349 #interrupt-cells = <2>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&ps_hold>;
361 intc: interrupt-controller@2000000 {
362 compatible = "qcom,msm-qgic2";
363 interrupt-controller;
364 #interrupt-cells = <3>;
370 compatible = "qcom,kpss-timer",
371 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
376 clock-frequency = <27000000>,
378 cpu-offset = <0x80000>;
381 acc0: clock-controller@2088000 {
382 compatible = "qcom,kpss-acc-v1";
386 acc1: clock-controller@2098000 {
387 compatible = "qcom,kpss-acc-v1";
391 acc2: clock-controller@20a8000 {
392 compatible = "qcom,kpss-acc-v1";
396 acc3: clock-controller@20b8000 {
397 compatible = "qcom,kpss-acc-v1";
401 saw0: power-controller@2089000 {
402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
407 saw1: power-controller@2099000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
413 saw2: power-controller@20a9000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
419 saw3: power-controller@20b9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
425 sps_sic_non_secure: sps-sic-non-secure@12100000 {
432 compatible = "qcom,gsbi-v1.0.0";
433 cell-index = <1>;
435 clocks = <&gcc GSBI1_H_CLK>;
436 clock-names = "iface";
437 #address-cells = <1>;
438 #size-cells = <1>;
441 syscon-tcsr = <&tcsr>;
444 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
448 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
449 clock-names = "core", "iface";
454 compatible = "qcom,i2c-qup-v1.1.1";
455 pinctrl-0 = <&i2c1_pins>;
456 pinctrl-1 = <&i2c1_pins_sleep>;
457 pinctrl-names = "default", "sleep";
460 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
461 clock-names = "core", "iface";
462 #address-cells = <1>;
463 #size-cells = <0>;
471 compatible = "qcom,gsbi-v1.0.0";
472 cell-index = <2>;
474 clocks = <&gcc GSBI2_H_CLK>;
475 clock-names = "iface";
476 #address-cells = <1>;
477 #size-cells = <1>;
480 syscon-tcsr = <&tcsr>;
483 compatible = "qcom,i2c-qup-v1.1.1";
485 pinctrl-0 = <&i2c2_pins>;
486 pinctrl-1 = <&i2c2_pins_sleep>;
487 pinctrl-names = "default", "sleep";
489 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
490 clock-names = "core", "iface";
491 #address-cells = <1>;
492 #size-cells = <0>;
499 compatible = "qcom,gsbi-v1.0.0";
500 cell-index = <3>;
502 clocks = <&gcc GSBI3_H_CLK>;
503 clock-names = "iface";
504 #address-cells = <1>;
505 #size-cells = <1>;
508 compatible = "qcom,i2c-qup-v1.1.1";
509 pinctrl-0 = <&i2c3_pins>;
510 pinctrl-1 = <&i2c3_pins_sleep>;
511 pinctrl-names = "default", "sleep";
514 clocks = <&gcc GSBI3_QUP_CLK>,
515 <&gcc GSBI3_H_CLK>;
516 clock-names = "core", "iface";
517 #address-cells = <1>;
518 #size-cells = <0>;
525 compatible = "qcom,gsbi-v1.0.0";
526 cell-index = <4>;
528 clocks = <&gcc GSBI4_H_CLK>;
529 clock-names = "iface";
530 #address-cells = <1>;
531 #size-cells = <1>;
535 compatible = "qcom,i2c-qup-v1.1.1";
536 pinctrl-0 = <&i2c4_pins>;
537 pinctrl-1 = <&i2c4_pins_sleep>;
538 pinctrl-names = "default", "sleep";
541 clocks = <&gcc GSBI4_QUP_CLK>,
542 <&gcc GSBI4_H_CLK>;
543 clock-names = "core", "iface";
550 compatible = "qcom,gsbi-v1.0.0";
551 cell-index = <5>;
553 clocks = <&gcc GSBI5_H_CLK>;
554 clock-names = "iface";
555 #address-cells = <1>;
556 #size-cells = <1>;
560 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
564 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
565 clock-names = "core", "iface";
570 compatible = "qcom,spi-qup-v1.1.1";
573 pinctrl-0 = <&spi5_default>;
574 pinctrl-1 = <&spi5_sleep>;
575 pinctrl-names = "default", "sleep";
576 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
577 clock-names = "core", "iface";
579 #address-cells = <1>;
580 #size-cells = <0>;
586 compatible = "qcom,gsbi-v1.0.0";
587 cell-index = <6>;
589 clocks = <&gcc GSBI6_H_CLK>;
590 clock-names = "iface";
591 #address-cells = <1>;
592 #size-cells = <1>;
596 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
600 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
601 clock-names = "core", "iface";
606 compatible = "qcom,i2c-qup-v1.1.1";
607 pinctrl-0 = <&i2c6_pins>;
608 pinctrl-1 = <&i2c6_pins_sleep>;
609 pinctrl-names = "default", "sleep";
612 clocks = <&gcc GSBI6_QUP_CLK>,
613 <&gcc GSBI6_H_CLK>;
614 clock-names = "core", "iface";
621 compatible = "qcom,gsbi-v1.0.0";
622 cell-index = <7>;
624 clocks = <&gcc GSBI7_H_CLK>;
625 clock-names = "iface";
626 #address-cells = <1>;
627 #size-cells = <1>;
629 syscon-tcsr = <&tcsr>;
632 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
636 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
637 clock-names = "core", "iface";
642 compatible = "qcom,i2c-qup-v1.1.1";
643 pinctrl-0 = <&i2c7_pins>;
644 pinctrl-1 = <&i2c7_pins_sleep>;
645 pinctrl-names = "default", "sleep";
648 clocks = <&gcc GSBI7_QUP_CLK>,
649 <&gcc GSBI7_H_CLK>;
650 clock-names = "core", "iface";
658 clocks = <&gcc PRNG_CLK>;
659 clock-names = "core";
665 qcom,controller-type = "pmic-arbiter";
669 interrupt-parent = <&tlmm_pinmux>;
671 #interrupt-cells = <2>;
672 interrupt-controller;
673 #address-cells = <1>;
674 #size-cells = <0>;
677 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
683 gpio-controller;
684 #gpio-cells = <2>;
692 qcom,controller-type = "pmic-arbiter";
696 interrupt-parent = <&tlmm_pinmux>;
698 #interrupt-cells = <2>;
699 interrupt-controller;
700 #address-cells = <1>;
701 #size-cells = <0>;
705 compatible = "qcom,pm8921-gpio",
706 "qcom,ssbi-gpio";
752 gpio-controller;
753 #gpio-cells = <2>;
758 compatible = "qcom,pm8921-mpp",
759 "qcom,ssbi-mpp";
761 gpio-controller;
762 #gpio-cells = <2>;
779 compatible = "qcom,pm8921-rtc";
780 interrupt-parent = <&pmicintc>;
783 allow-set-time;
787 compatible = "qcom,pm8921-pwrkey";
789 interrupt-parent = <&pmicintc>;
792 pull-up;
796 compatible = "qcom,pm8921-adc";
798 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
799 #address-cells = <2>;
800 #size-cells = <0>;
801 #io-channel-cells = <2>;
803 vcoin: adc-channel@00 {
806 vbat: adc-channel@01 {
809 dcin: adc-channel@02 {
812 vph_pwr: adc-channel@04 {
815 batt_therm: adc-channel@08 {
818 batt_id: adc-channel@09 {
821 usb_vbus: adc-channel@0a {
824 die_temp: adc-channel@0b {
827 ref_625mv: adc-channel@0c {
830 ref_1250mv: adc-channel@0d {
833 chg_temp: adc-channel@0e {
836 ref_muxoff: adc-channel@0f {
846 #address-cells = <1>;
847 #size-cells = <1>;
857 gcc: clock-controller@900000 { label
858 compatible = "qcom,gcc-apq8064";
860 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
861 nvmem-cell-names = "calib", "calib_backup";
862 #clock-cells = <1>;
863 #reset-cells = <1>;
864 #thermal-sensor-cells = <1>;
867 lcc: clock-controller@28000000 {
868 compatible = "qcom,lcc-apq8064";
870 #clock-cells = <1>;
871 #reset-cells = <1>;
874 mmcc: clock-controller@4000000 {
875 compatible = "qcom,mmcc-apq8064";
877 #clock-cells = <1>;
878 #reset-cells = <1>;
881 l2cc: clock-controller@2011000 {
887 compatible = "qcom,rpm-apq8064";
894 interrupt-names = "ack", "err", "wakeup";
896 rpmcc: clock-controller {
897 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
898 #clock-cells = <1>;
902 compatible = "qcom,rpm-pm8921-regulators";
946 pm8921_usb_switch: usb-switch {};
948 pm8921_hdmi_switch: hdmi-switch {
949 bias-pull-down;
957 compatible = "qcom,ci-hdrc";
961 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
962 clock-names = "core", "iface";
963 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
964 assigned-clock-rates = <60000000>;
965 resets = <&gcc USB_HS1_RESET>;
966 reset-names = "core";
968 ahb-burst-config = <0>;
970 phy-names = "usb-phy";
972 #reset-cells = <1>;
976 compatible = "qcom,usb-hs-phy-apq8064",
977 "qcom,usb-hs-phy";
979 clock-names = "sleep", "ref";
981 reset-names = "por";
982 #phy-cells = <0>;
988 compatible = "qcom,ci-hdrc";
992 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
993 clock-names = "core", "iface";
994 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
995 assigned-clock-rates = <60000000>;
996 resets = <&gcc USB_HS3_RESET>;
997 reset-names = "core";
999 ahb-burst-config = <0>;
1001 phy-names = "usb-phy";
1003 #reset-cells = <1>;
1007 compatible = "qcom,usb-hs-phy-apq8064",
1008 "qcom,usb-hs-phy";
1009 #phy-cells = <0>;
1011 clock-names = "sleep", "ref";
1013 reset-names = "por";
1019 compatible = "qcom,ci-hdrc";
1023 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1024 clock-names = "core", "iface";
1025 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1026 assigned-clock-rates = <60000000>;
1027 resets = <&gcc USB_HS4_RESET>;
1028 reset-names = "core";
1030 ahb-burst-config = <0>;
1032 phy-names = "usb-phy";
1034 #reset-cells = <1>;
1038 compatible = "qcom,usb-hs-phy-apq8064",
1039 "qcom,usb-hs-phy";
1040 #phy-cells = <0>;
1042 clock-names = "sleep", "ref";
1044 reset-names = "por";
1050 compatible = "qcom,apq8064-sata-phy";
1053 reg-names = "phy_mem";
1054 clocks = <&gcc SATA_PHY_CFG_CLK>;
1055 clock-names = "cfg";
1056 #phy-cells = <0>;
1060 compatible = "qcom,apq8064-ahci", "generic-ahci";
1065 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1066 <&gcc SATA_H_CLK>,
1067 <&gcc SATA_A_CLK>,
1068 <&gcc SATA_RXOOB_CLK>,
1069 <&gcc SATA_PMALIVE_CLK>;
1070 clock-names = "slave_iface",
1076 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1077 <&gcc SATA_PMALIVE_CLK>;
1078 assigned-clock-rates = <100000000>, <100000000>;
1081 phy-names = "sata-phy";
1082 ports-implemented = <0x1>;
1087 compatible = "qcom,bam-v1.3.0";
1090 clocks = <&gcc SDC1_H_CLK>;
1091 clock-names = "bam_clk";
1092 #dma-cells = <1>;
1097 compatible = "qcom,bam-v1.3.0";
1100 clocks = <&gcc SDC3_H_CLK>;
1101 clock-names = "bam_clk";
1102 #dma-cells = <1>;
1107 compatible = "qcom,bam-v1.3.0";
1110 clocks = <&gcc SDC4_H_CLK>;
1111 clock-names = "bam_clk";
1112 #dma-cells = <1>;
1117 compatible = "simple-bus";
1118 #address-cells = <1>;
1119 #size-cells = <1>;
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&sdcc1_pins>;
1126 arm,primecell-periphid = <0x00051180>;
1129 interrupt-names = "cmd_irq";
1130 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1131 clock-names = "mclk", "apb_pclk";
1132 bus-width = <8>;
1133 max-frequency = <96000000>;
1134 non-removable;
1135 cap-sd-highspeed;
1136 cap-mmc-highspeed;
1138 dma-names = "tx", "rx";
1143 arm,primecell-periphid = <0x00051180>;
1147 interrupt-names = "cmd_irq";
1148 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1149 clock-names = "mclk", "apb_pclk";
1150 bus-width = <4>;
1151 cap-sd-highspeed;
1152 cap-mmc-highspeed;
1153 max-frequency = <192000000>;
1154 no-1-8-v;
1156 dma-names = "tx", "rx";
1161 arm,primecell-periphid = <0x00051180>;
1165 interrupt-names = "cmd_irq";
1166 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1167 clock-names = "mclk", "apb_pclk";
1168 bus-width = <4>;
1169 cap-sd-highspeed;
1170 cap-mmc-highspeed;
1171 max-frequency = <48000000>;
1173 dma-names = "tx", "rx";
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&sdc4_gpios>;
1180 compatible = "qcom,tcsr-apq8064", "syscon";
1184 gpu: adreno-3xx@4300000 {
1185 compatible = "qcom,adreno-3xx";
1187 reg-names = "kgsl_3d0_reg_memory";
1189 interrupt-names = "kgsl_3d0_irq";
1190 clock-names =
1267 qcom,gpu-pwrlevels {
1268 compatible = "qcom,gpu-pwrlevels";
1269 qcom,gpu-pwrlevel@0 {
1270 qcom,gpu-freq = <450000000>;
1272 qcom,gpu-pwrlevel@1 {
1273 qcom,gpu-freq = <27000000>;
1284 compatible = "qcom,mdss-dsi-ctrl";
1285 label = "MDSS DSI CTRL->0";
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1290 reg-names = "dsi_ctrl";
1299 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1303 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1307 assigned-clock-parents = <&dsi0_phy 0>,
1311 syscon-sfpb = <&mmss_sfpb>;
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1332 dsi0_phy: dsi-phy@4700200 {
1333 compatible = "qcom,dsi-phy-28nm-8960";
1334 #clock-cells = <1>;
1335 #phy-cells = <0>;
1340 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1341 clock-names = "iface_clk";
1347 compatible = "qcom,apq8064-iommu";
1348 #iommu-cells = <1>;
1349 clock-names =
1363 compatible = "qcom,apq8064-iommu";
1364 #iommu-cells = <1>;
1365 clock-names =
1379 compatible = "qcom,apq8064-iommu";
1380 #iommu-cells = <1>;
1381 clock-names =
1395 compatible = "qcom,apq8064-iommu";
1396 #iommu-cells = <1>;
1397 clock-names =
1411 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1416 reg-names = "dbi", "elbi", "parf", "config";
1418 linux,pci-domain = <0>;
1419 bus-range = <0x00 0xff>;
1420 num-lanes = <1>;
1421 #address-cells = <3>;
1422 #size-cells = <2>;
1426 interrupt-names = "msi";
1427 #interrupt-cells = <1>;
1428 interrupt-map-mask = <0 0 0 0x7>;
1429 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1433 clocks = <&gcc PCIE_A_CLK>,
1434 <&gcc PCIE_H_CLK>,
1435 <&gcc PCIE_PHY_REF_CLK>;
1436 clock-names = "core", "iface", "phy";
1437 resets = <&gcc PCIE_ACLK_RESET>,
1438 <&gcc PCIE_HCLK_RESET>,
1439 <&gcc PCIE_POR_RESET>,
1440 <&gcc PCIE_PCI_RESET>,
1441 <&gcc PCIE_PHY_RESET>;
1442 reset-names = "axi", "ahb", "por", "pci", "phy";
1446 hdmi: hdmi-tx@4a00000 {
1447 compatible = "qcom,hdmi-tx-8960";
1448 pinctrl-names = "default";
1449 pinctrl-0 = <&hdmi_pinctrl>;
1451 reg-names = "core_physical";
1456 clock-names = "core_clk",
1461 phy-names = "hdmi-phy";
1464 #address-cells = <1>;
1465 #size-cells = <0>;
1481 hdmi_phy: hdmi-phy@4a00400 {
1482 compatible = "qcom,hdmi-phy-8960";
1485 reg-names = "hdmi_phy",
1489 clock-names = "slave_iface_clk";
1490 #phy-cells = <0>;
1503 clock-names = "core_clk",
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1545 riva: riva-pil@3204000 {
1546 compatible = "qcom,riva-pil";
1549 reg-names = "ccu", "dxe", "pmu";
1551 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1553 interrupt-names = "wdog", "fatal";
1555 memory-region = <&wcnss_mem>;
1557 vddcx-supply = <&pm8921_s3>;
1558 vddmx-supply = <&pm8921_l24>;
1559 vddpx-supply = <&pm8921_s4>;
1567 clock-names = "xo";
1569 vddxo-supply = <&pm8921_l4>;
1570 vddrfa-supply = <&pm8921_s2>;
1571 vddpa-supply = <&pm8921_l10>;
1572 vdddig-supply = <&pm8921_lvs2>;
1575 smd-edge {
1579 qcom,smd-edge = <6>;
1585 qcom,smd-channels = "WCNSS_CTRL";
1590 compatible = "qcom,wcnss-bt";
1594 compatible = "qcom,wcnss-wlan";
1598 interrupt-names = "tx", "rx";
1600 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1601 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1608 compatible = "coresight-etb10", "arm,primecell";
1612 clock-names = "apb_pclk";
1616 slave-mode;
1617 remote-endpoint = <&replicator_out0>;
1623 compatible = "arm,coresight-tpiu", "arm,primecell";
1627 clock-names = "apb_pclk";
1631 slave-mode;
1632 remote-endpoint = <&replicator_out1>;
1638 compatible = "arm,coresight-replicator";
1641 clock-names = "apb_pclk";
1644 #address-cells = <1>;
1645 #size-cells = <0>;
1650 remote-endpoint = <&etb_in>;
1656 remote-endpoint = <&tpiu_in>;
1662 slave-mode;
1663 remote-endpoint = <&funnel_out>;
1670 compatible = "arm,coresight-funnel", "arm,primecell";
1674 clock-names = "apb_pclk";
1677 #address-cells = <1>;
1678 #size-cells = <0>;
1682 * 2 - connected to STM component
1683 * 3 - not-connected
1684 * 6 - not-connected
1685 * 7 - not-connected
1690 slave-mode;
1691 remote-endpoint = <&etm0_out>;
1697 slave-mode;
1698 remote-endpoint = <&etm1_out>;
1704 slave-mode;
1705 remote-endpoint = <&etm2_out>;
1711 slave-mode;
1712 remote-endpoint = <&etm3_out>;
1718 remote-endpoint = <&replicator_in>;
1725 compatible = "arm,coresight-etm3x", "arm,primecell";
1729 clock-names = "apb_pclk";
1735 remote-endpoint = <&funnel_in0>;
1741 compatible = "arm,coresight-etm3x", "arm,primecell";
1745 clock-names = "apb_pclk";
1751 remote-endpoint = <&funnel_in1>;
1757 compatible = "arm,coresight-etm3x", "arm,primecell";
1761 clock-names = "apb_pclk";
1767 remote-endpoint = <&funnel_in4>;
1773 compatible = "arm,coresight-etm3x", "arm,primecell";
1777 clock-names = "apb_pclk";
1783 remote-endpoint = <&funnel_in5>;
1789 #include "qcom-apq8064-pins.dtsi"