Lines Matching full:gcc
17 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
59 clocks = <&gcc GCC_APPS_CLK_SRC>;
78 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clocks = <&gcc GCC_APPS_CLK_SRC>;
116 clocks = <&gcc GCC_APPS_CLK_SRC>;
178 gcc: clock-controller@1800000 { label
179 compatible = "qcom,gcc-ipq4019";
188 clocks = <&gcc GCC_PRNG_AHB_CLK>;
207 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
218 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
219 <&gcc GCC_BLSP1_AHB_CLK>;
232 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
233 <&gcc GCC_BLSP1_AHB_CLK>;
246 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
247 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
260 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
261 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
274 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
285 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
286 <&gcc GCC_CRYPTO_AXI_CLK>,
287 <&gcc GCC_CRYPTO_CLK>;
343 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
344 <&gcc GCC_BLSP1_AHB_CLK>;
355 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
356 <&gcc GCC_BLSP1_AHB_CLK>;
400 clocks = <&gcc GCC_PCIE_AHB_CLK>,
401 <&gcc GCC_PCIE_AXI_M_CLK>,
402 <&gcc GCC_PCIE_AXI_S_CLK>;
407 resets = <&gcc PCIE_AXI_M_ARES>,
408 <&gcc PCIE_AXI_S_ARES>,
409 <&gcc PCIE_PIPE_ARES>,
410 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
411 <&gcc PCIE_AXI_S_XPU_ARES>,
412 <&gcc PCIE_PARF_XPU_ARES>,
413 <&gcc PCIE_PHY_ARES>,
414 <&gcc PCIE_AXI_M_STICKY_ARES>,
415 <&gcc PCIE_PIPE_STICKY_ARES>,
416 <&gcc PCIE_PWR_ARES>,
417 <&gcc PCIE_AHB_ARES>,
418 <&gcc PCIE_PHY_AHB_ARES>;
439 clocks = <&gcc GCC_QPIC_CLK>;
451 clocks = <&gcc GCC_QPIC_CLK>,
452 <&gcc GCC_QPIC_AHB_CLK>;
473 resets = <&gcc WIFI0_CPU_INIT_RESET>,
474 <&gcc WIFI0_RADIO_SRIF_RESET>,
475 <&gcc WIFI0_RADIO_WARM_RESET>,
476 <&gcc WIFI0_RADIO_COLD_RESET>,
477 <&gcc WIFI0_CORE_WARM_RESET>,
478 <&gcc WIFI0_CORE_COLD_RESET>;
482 clocks = <&gcc GCC_WCSS2G_CLK>,
483 <&gcc GCC_WCSS2G_REF_CLK>,
484 <&gcc GCC_WCSS2G_RTC_CLK>;
515 resets = <&gcc WIFI1_CPU_INIT_RESET>,
516 <&gcc WIFI1_RADIO_SRIF_RESET>,
517 <&gcc WIFI1_RADIO_WARM_RESET>,
518 <&gcc WIFI1_RADIO_COLD_RESET>,
519 <&gcc WIFI1_CORE_WARM_RESET>,
520 <&gcc WIFI1_CORE_COLD_RESET>;
524 clocks = <&gcc GCC_WCSS5G_CLK>,
525 <&gcc GCC_WCSS5G_REF_CLK>,
526 <&gcc GCC_WCSS5G_RTC_CLK>;