Lines Matching +full:kpss +full:- +full:acc
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
16 #address-cells = <1>;
17 #size-cells = <0>;
21 enable-method = "qcom,kpss-acc-v1";
24 next-level-cache = <&L2>;
25 qcom,acc = <&acc0>;
31 enable-method = "qcom,kpss-acc-v1";
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc1>;
39 L2: l2-cache {
41 cache-level = <2>;
45 cpu-pmu {
46 compatible = "qcom,krait-pmu";
51 reserved-memory {
52 #address-cells = <1>;
53 #size-cells = <1>;
58 no-map;
63 no-map;
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <25000000>;
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <25000000>;
81 compatible = "fixed-clock";
82 clock-frequency = <32768>;
83 #clock-cells = <0>;
88 #address-cells = <1>;
89 #size-cells = <1>;
91 compatible = "simple-bus";
94 compatible = "qcom,lpass-cpu";
99 clock-names = "ahbix-clk",
100 "mi2s-osr-clk",
101 "mi2s-bit-clk";
103 interrupt-names = "lpass-irq-lpaif";
105 reg-names = "lpass-lpaif";
109 compatible = "qcom,ipq8064-pinctrl";
112 gpio-controller;
113 #gpio-cells = <2>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
119 intc: interrupt-controller@2000000 {
120 compatible = "qcom,msm-qgic2";
121 interrupt-controller;
122 #interrupt-cells = <3>;
128 compatible = "qcom,kpss-timer",
129 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
141 clock-frequency = <25000000>,
144 clock-names = "sleep";
145 cpu-offset = <0x80000>;
148 acc0: clock-controller@2088000 {
149 compatible = "qcom,kpss-acc-v1";
153 acc1: clock-controller@2098000 {
154 compatible = "qcom,kpss-acc-v1";
171 compatible = "qcom,gsbi-v1.0.0";
172 cell-index = <2>;
175 clock-names = "iface";
176 #address-cells = <1>;
177 #size-cells = <1>;
181 syscon-tcsr = <&tcsr>;
184 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
189 clock-names = "core", "iface";
194 compatible = "qcom,i2c-qup-v1.1.1";
199 clock-names = "core", "iface";
202 #address-cells = <1>;
203 #size-cells = <0>;
209 compatible = "qcom,gsbi-v1.0.0";
210 cell-index = <4>;
213 clock-names = "iface";
214 #address-cells = <1>;
215 #size-cells = <1>;
219 syscon-tcsr = <&tcsr>;
222 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
227 clock-names = "core", "iface";
232 compatible = "qcom,i2c-qup-v1.1.1";
237 clock-names = "core", "iface";
240 #address-cells = <1>;
241 #size-cells = <0>;
246 compatible = "qcom,gsbi-v1.0.0";
247 cell-index = <5>;
250 clock-names = "iface";
251 #address-cells = <1>;
252 #size-cells = <1>;
256 syscon-tcsr = <&tcsr>;
259 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
264 clock-names = "core", "iface";
269 compatible = "qcom,i2c-qup-v1.1.1";
274 clock-names = "core", "iface";
277 #address-cells = <1>;
278 #size-cells = <0>;
282 compatible = "qcom,spi-qup-v1.1.1";
287 clock-names = "core", "iface";
290 #address-cells = <1>;
291 #size-cells = <0>;
297 compatible = "qcom,gsbi-v1.0.0";
298 cell-index = <7>;
301 clock-names = "iface";
302 #address-cells = <1>;
303 #size-cells = <1>;
305 syscon-tcsr = <&tcsr>;
308 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
313 clock-names = "core", "iface";
318 sata_phy: sata-phy@1b400000 {
319 compatible = "qcom,ipq806x-sata-phy";
323 clock-names = "cfg";
325 #phy-cells = <0>;
330 compatible = "qcom,ipq806x-ahci", "generic-ahci";
340 clock-names = "slave_face", "iface", "core",
343 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
344 assigned-clock-rates = <100000000>, <100000000>;
347 phy-names = "sata-phy";
354 qcom,controller-type = "pmic-arbiter";
357 gcc: clock-controller@900000 {
358 compatible = "qcom,gcc-ipq8064";
360 #clock-cells = <1>;
361 #reset-cells = <1>;
365 compatible = "qcom,tcsr-ipq8064", "syscon";
369 lcc: clock-controller@28000000 {
370 compatible = "qcom,lcc-ipq8064";
372 #clock-cells = <1>;
373 #reset-cells = <1>;