Lines Matching +full:0 +full:x400
56 #clock-cells = <0>;
58 clock-frequency = <0>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
74 #clock-cells = <0>;
76 clock-frequency = <0>;
83 reg = <0x40000000 0x400>;
85 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
91 #size-cells = <0>;
93 reg = <0x40000000 0x400>;
94 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
112 reg = <0x40000400 0x400>;
114 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
120 #size-cells = <0>;
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
141 reg = <0x40000800 0x400>;
143 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
149 #size-cells = <0>;
151 reg = <0x40000800 0x400>;
152 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
170 reg = <0x40000c00 0x400>;
172 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
177 #size-cells = <0>;
179 reg = <0x40000C00 0x400>;
180 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
198 reg = <0x40001000 0x400>;
200 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
206 #size-cells = <0>;
208 reg = <0x40001000 0x400>;
209 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
222 reg = <0x40001400 0x400>;
224 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
230 #size-cells = <0>;
232 reg = <0x40001400 0x400>;
233 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
246 #size-cells = <0>;
248 reg = <0x40001800 0x400>;
249 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
267 #size-cells = <0>;
269 reg = <0x40001C00 0x400>;
270 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
282 #size-cells = <0>;
284 reg = <0x40002000 0x400>;
285 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
297 reg = <0x40002800 0x400>;
305 st,syscfg = <&pwrcfg 0x00 0x100>;
311 reg = <0x40003000 0x400>;
319 reg = <0x40004400 0x400>;
321 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
327 reg = <0x40004800 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
331 dmas = <&dma1 1 4 0x400 0x0>,
332 <&dma1 3 4 0x400 0x0>;
338 reg = <0x40004c00 0x400>;
340 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
346 reg = <0x40005000 0x400>;
348 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
354 reg = <0x40005400 0x400>;
358 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
360 #size-cells = <0>;
366 reg = <0x40007400 0x400>;
368 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
371 #size-cells = <0>;
391 reg = <0x40007800 0x400>;
393 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
399 reg = <0x40007c00 0x400>;
401 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
407 #size-cells = <0>;
409 reg = <0x40010000 0x400>;
410 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
419 timer@0 {
421 reg = <0>;
428 #size-cells = <0>;
430 reg = <0x40010400 0x400>;
431 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
449 reg = <0x40011000 0x400>;
451 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
453 dmas = <&dma2 2 4 0x400 0x0>,
454 <&dma2 7 4 0x400 0x0>;
460 reg = <0x40011400 0x400>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
468 reg = <0x40012000 0x400>;
470 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
475 #size-cells = <0>;
478 adc1: adc@0 {
481 reg = <0x0>;
482 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
484 interrupts = <0>;
485 dmas = <&dma2 0 0 0x400 0x0>;
493 reg = <0x100>;
494 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
497 dmas = <&dma2 3 1 0x400 0x0>;
505 reg = <0x200>;
506 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
509 dmas = <&dma2 1 2 0x400 0x0>;
517 arm,primecell-periphid = <0x00880180>;
518 reg = <0x40012c00 0x400>;
519 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
528 reg = <0x40013800 0x400>;
535 reg = <0x40013C00 0x400>;
541 #size-cells = <0>;
543 reg = <0x40014000 0x400>;
544 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
562 #size-cells = <0>;
564 reg = <0x40014400 0x400>;
565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
577 #size-cells = <0>;
579 reg = <0x40014800 0x400>;
580 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
592 reg = <0x40007000 0x400>;
597 reg = <0x40016800 0x200>;
607 reg = <0x40023000 0x400>;
608 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
616 reg = <0x40023800 0x400>;
625 reg = <0x40026000 0x400>;
634 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
640 reg = <0x40026400 0x400>;
649 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
656 reg = <0x40028000 0x8000>;
661 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
662 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
663 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
664 st,syscon = <&syscfg 0x4>;
672 reg = <0x40040000 0x40000>;
674 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
681 reg = <0x50000000 0x40000>;
683 clocks = <&rcc 0 39>;
690 reg = <0x50050000 0x400>;
693 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
696 pinctrl-0 = <&dcmi_pins>;
697 dmas = <&dma2 1 1 0x414 0x3>;
704 reg = <0x50060800 0x400>;
706 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;