Lines Matching +full:0 +full:x400
51 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
69 #clock-cells = <0>;
78 reg = <0x40000000 0x400>;
80 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
86 #size-cells = <0>;
88 reg = <0x40000000 0x400>;
89 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
107 reg = <0x40000400 0x400>;
109 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
115 #size-cells = <0>;
117 reg = <0x40000400 0x400>;
118 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
136 reg = <0x40000800 0x400>;
138 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
144 #size-cells = <0>;
146 reg = <0x40000800 0x400>;
147 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
165 reg = <0x40000c00 0x400>;
167 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
172 #size-cells = <0>;
174 reg = <0x40000C00 0x400>;
175 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
193 reg = <0x40001000 0x400>;
195 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
201 #size-cells = <0>;
203 reg = <0x40001000 0x400>;
204 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
217 reg = <0x40001400 0x400>;
219 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
225 #size-cells = <0>;
227 reg = <0x40001400 0x400>;
228 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
241 #size-cells = <0>;
243 reg = <0x40001800 0x400>;
244 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
262 #size-cells = <0>;
264 reg = <0x40001C00 0x400>;
265 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
277 #size-cells = <0>;
279 reg = <0x40002000 0x400>;
280 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
292 reg = <0x40002800 0x400>;
300 st,syscfg = <&pwrcfg 0x00 0x100>;
306 reg = <0x40004400 0x400>;
314 reg = <0x40004800 0x400>;
322 reg = <0x40004c00 0x400>;
330 reg = <0x40005000 0x400>;
338 reg = <0x40005400 0x400>;
344 #size-cells = <0>;
350 reg = <0x40005800 0x400>;
356 #size-cells = <0>;
362 reg = <0x40005C00 0x400>;
368 #size-cells = <0>;
374 reg = <0x40006000 0x400>;
380 #size-cells = <0>;
386 reg = <0x40006C00 0x400>;
388 clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
395 reg = <0x40007800 0x400>;
403 reg = <0x40007c00 0x400>;
411 #size-cells = <0>;
413 reg = <0x40010000 0x400>;
414 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM1)>;
423 timer@0 {
425 reg = <0>;
432 #size-cells = <0>;
434 reg = <0x40010400 0x400>;
435 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM8)>;
453 reg = <0x40011000 0x400>;
461 reg = <0x40011400 0x400>;
469 arm,primecell-periphid = <0x00880180>;
470 reg = <0x40011c00 0x400>;
471 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC2)>;
480 arm,primecell-periphid = <0x00880180>;
481 reg = <0x40012c00 0x400>;
482 clocks = <&rcc 0 STM32F7_APB2_CLOCK(SDMMC1)>;
491 reg = <0x40013800 0x400>;
498 reg = <0x40013C00 0x400>;
504 #size-cells = <0>;
506 reg = <0x40014000 0x400>;
507 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM9)>;
525 #size-cells = <0>;
527 reg = <0x40014400 0x400>;
528 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
540 #size-cells = <0>;
542 reg = <0x40014800 0x400>;
543 clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
555 reg = <0x40007000 0x400>;
560 reg = <0x40023000 0x400>;
561 clocks = <&rcc 0 12>;
569 reg = <0x40023800 0x400>;
578 reg = <0x40026000 0x400>;
587 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA1)>;
594 reg = <0x40026400 0x400>;
603 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(DMA2)>;
611 reg = <0x40040000 0x40000>;
613 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHS)>;
623 reg = <0x50000000 0x40000>;
625 clocks = <&rcc 0 STM32F7_AHB2_CLOCK(OTGFS)>;
633 clocks = <&rcc 1 0>;