Lines Matching +full:1 +full:c00

85 			#address-cells = <1>;
98 			timer@1 {
100 				reg = <1>;
114 			#address-cells = <1>;
143 			#address-cells = <1>;
163 		timer5: timer@40000c00 {
170 		timers5: timers@40000c00 {
171 			#address-cells = <1>;
200 			#address-cells = <1>;
224 			#address-cells = <1>;
240 			#address-cells = <1>;
260 		timers13: timers@40001c00 {
261 			#address-cells = <1>;
276 			#address-cells = <1>;
293 			clocks = <&rcc 1 CLK_RTC>;
295 			assigned-clocks = <&rcc 1 CLK_RTC>;
296 			assigned-clock-parents = <&rcc 1 CLK_LSE>;
298 			interrupts = <17 1>;
308 			clocks = <&rcc 1 CLK_USART2>;
316 			clocks = <&rcc 1 CLK_USART3>;
320 		usart4: serial@40004c00 {
324 			clocks = <&rcc 1 CLK_UART4>;
332 			clocks = <&rcc 1 CLK_UART5>;
342 			clocks = <&rcc 1 CLK_I2C1>;
343 			#address-cells = <1>;
354 			clocks = <&rcc 1 CLK_I2C2>;
355 			#address-cells = <1>;
360 		i2c3: i2c@40005C00 {
366 			clocks = <&rcc 1 CLK_I2C3>;
367 			#address-cells = <1>;
378 			clocks = <&rcc 1 CLK_I2C4>;
379 			#address-cells = <1>;
384 		cec: cec@40006c00 {
388 			clocks = <&rcc 0 STM32F7_APB1_CLOCK(CEC)>, <&rcc 1 CLK_HDMI_CEC>;
397 			clocks = <&rcc 1 CLK_UART7>;
401 		usart8: serial@40007c00 {
405 			clocks = <&rcc 1 CLK_UART8>;
410 			#address-cells = <1>;
431 			#address-cells = <1>;
455 			clocks = <&rcc 1 CLK_USART1>;
463 			clocks = <&rcc 1 CLK_USART6>;
467 		sdio2: sdio2@40011c00 {
478 		sdio1: sdio1@40012c00 {
494 		exti: interrupt-controller@40013c00 {
499 			interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
503 			#address-cells = <1>;
524 			#address-cells = <1>;
539 			#address-cells = <1>;
566 			#reset-cells = <1>;
572 			assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
633 	clocks = <&rcc 1 0>;