Lines Matching +full:uniphier +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 // Device Tree Source for UniPhier Pro5 SoC
5 // Copyright (C) 2015-2016 Socionext Inc.
9 compatible = "socionext,uniphier-pro5";
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
22 enable-method = "psci";
23 next-level-cache = <&l2>;
24 operating-points-v2 = <&cpu_opp>;
29 compatible = "arm,cortex-a9";
32 enable-method = "psci";
33 next-level-cache = <&l2>;
34 operating-points-v2 = <&cpu_opp>;
38 cpu_opp: opp-table {
39 compatible = "operating-points-v2";
40 opp-shared;
42 opp-100000000 {
43 opp-hz = /bits/ 64 <100000000>;
44 clock-latency-ns = <300>;
46 opp-116667000 {
47 opp-hz = /bits/ 64 <116667000>;
48 clock-latency-ns = <300>;
50 opp-150000000 {
51 opp-hz = /bits/ 64 <150000000>;
52 clock-latency-ns = <300>;
54 opp-175000000 {
55 opp-hz = /bits/ 64 <175000000>;
56 clock-latency-ns = <300>;
58 opp-200000000 {
59 opp-hz = /bits/ 64 <200000000>;
60 clock-latency-ns = <300>;
62 opp-233334000 {
63 opp-hz = /bits/ 64 <233334000>;
64 clock-latency-ns = <300>;
66 opp-300000000 {
67 opp-hz = /bits/ 64 <300000000>;
68 clock-latency-ns = <300>;
70 opp-350000000 {
71 opp-hz = /bits/ 64 <350000000>;
72 clock-latency-ns = <300>;
74 opp-400000000 {
75 opp-hz = /bits/ 64 <400000000>;
76 clock-latency-ns = <300>;
78 opp-466667000 {
79 opp-hz = /bits/ 64 <466667000>;
80 clock-latency-ns = <300>;
82 opp-600000000 {
83 opp-hz = /bits/ 64 <600000000>;
84 clock-latency-ns = <300>;
86 opp-700000000 {
87 opp-hz = /bits/ 64 <700000000>;
88 clock-latency-ns = <300>;
90 opp-800000000 {
91 opp-hz = /bits/ 64 <800000000>;
92 clock-latency-ns = <300>;
94 opp-933334000 {
95 opp-hz = /bits/ 64 <933334000>;
96 clock-latency-ns = <300>;
98 opp-1200000000 {
99 opp-hz = /bits/ 64 <1200000000>;
100 clock-latency-ns = <300>;
102 opp-1400000000 {
103 opp-hz = /bits/ 64 <1400000000>;
104 clock-latency-ns = <300>;
109 compatible = "arm,psci-0.2";
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <20000000>;
120 arm_timer_clk: arm-timer {
121 #clock-cells = <0>;
122 compatible = "fixed-clock";
123 clock-frequency = <50000000>;
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
132 interrupt-parent = <&intc>;
134 l2: l2-cache@500c0000 {
135 compatible = "socionext,uniphier-system-cache";
139 cache-unified;
140 cache-size = <(2 * 1024 * 1024)>;
141 cache-sets = <512>;
142 cache-line-size = <128>;
143 cache-level = <2>;
144 next-level-cache = <&l3>;
147 l3: l3-cache@500c8000 {
148 compatible = "socionext,uniphier-system-cache";
152 cache-unified;
153 cache-size = <(2 * 1024 * 1024)>;
154 cache-sets = <512>;
155 cache-line-size = <256>;
156 cache-level = <3>;
160 compatible = "socionext,uniphier-uart";
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_uart0>;
171 compatible = "socionext,uniphier-uart";
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_uart1>;
182 compatible = "socionext,uniphier-uart";
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_uart2>;
193 compatible = "socionext,uniphier-uart";
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_uart3>;
204 compatible = "socionext,uniphier-gpio";
206 interrupt-parent = <&aidet>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 gpio-controller;
210 #gpio-cells = <2>;
211 gpio-ranges = <&pinctrl 0 0 0>;
212 gpio-ranges-group-names = "gpio_range";
214 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
217 i2c0: i2c@58780000 {
218 compatible = "socionext,uniphier-fi2c";
221 #address-cells = <1>;
222 #size-cells = <0>;
224 pinctrl-names = "default";
225 pinctrl-0 = <&pinctrl_i2c0>;
228 clock-frequency = <100000>;
231 i2c1: i2c@58781000 {
232 compatible = "socionext,uniphier-fi2c";
235 #address-cells = <1>;
236 #size-cells = <0>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_i2c1>;
242 clock-frequency = <100000>;
245 i2c2: i2c@58782000 {
246 compatible = "socionext,uniphier-fi2c";
249 #address-cells = <1>;
250 #size-cells = <0>;
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_i2c2>;
256 clock-frequency = <100000>;
259 i2c3: i2c@58783000 {
260 compatible = "socionext,uniphier-fi2c";
263 #address-cells = <1>;
264 #size-cells = <0>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_i2c3>;
270 clock-frequency = <100000>;
275 /* chip-internal connection for DMD */
276 i2c5: i2c@58785000 {
277 compatible = "socionext,uniphier-fi2c";
279 #address-cells = <1>;
280 #size-cells = <0>;
284 clock-frequency = <400000>;
287 /* chip-internal connection for HDMI */
288 i2c6: i2c@58786000 {
289 compatible = "socionext,uniphier-fi2c";
291 #address-cells = <1>;
292 #size-cells = <0>;
296 clock-frequency = <400000>;
299 system_bus: system-bus@58c00000 {
300 compatible = "socionext,uniphier-system-bus";
303 #address-cells = <2>;
304 #size-cells = <1>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_system_bus>;
310 compatible = "socionext,uniphier-smpctrl";
315 compatible = "socionext,uniphier-pro5-sdctrl",
316 "simple-mfd", "syscon";
320 compatible = "socionext,uniphier-pro5-sd-clock";
321 #clock-cells = <1>;
325 compatible = "socionext,uniphier-pro5-sd-reset";
326 #reset-cells = <1>;
331 compatible = "socionext,uniphier-pro5-perictrl",
332 "simple-mfd", "syscon";
336 compatible = "socionext,uniphier-pro5-peri-clock";
337 #clock-cells = <1>;
341 compatible = "socionext,uniphier-pro5-peri-reset";
342 #reset-cells = <1>;
346 soc-glue@5f800000 {
347 compatible = "socionext,uniphier-pro5-soc-glue",
348 "simple-mfd", "syscon";
352 compatible = "socionext,uniphier-pro5-pinctrl";
356 soc-glue@5f900000 {
357 compatible = "socionext,uniphier-pro5-soc-glue-debug",
358 "simple-mfd";
359 #address-cells = <1>;
360 #size-cells = <1>;
364 compatible = "socionext,uniphier-efuse";
369 compatible = "socionext,uniphier-efuse";
374 compatible = "socionext,uniphier-efuse";
379 compatible = "socionext,uniphier-efuse";
384 compatible = "socionext,uniphier-efuse";
390 compatible = "socionext,uniphier-pro5-aidet";
392 interrupt-controller;
393 #interrupt-cells = <2>;
397 compatible = "arm,cortex-a9-global-timer";
404 compatible = "arm,cortex-a9-twd-timer";
410 intc: interrupt-controller@60001000 {
411 compatible = "arm,cortex-a9-gic";
414 #interrupt-cells = <3>;
415 interrupt-controller;
419 compatible = "socionext,uniphier-pro5-sysctrl",
420 "simple-mfd", "syscon";
424 compatible = "socionext,uniphier-pro5-clock";
425 #clock-cells = <1>;
429 compatible = "socionext,uniphier-pro5-reset";
430 #reset-cells = <1>;
435 compatible = "socionext,uniphier-denali-nand-v5b";
437 reg-names = "nand_data", "denali_reg";
440 pinctrl-names = "default";
441 pinctrl-0 = <&pinctrl_nand2cs>;
448 #include "uniphier-pinctrl.dtsi"