Lines Matching +full:non +full:- +full:armv7

4  *  Copyright (C) 1999-2002 Russell King
15 #include <asm/glue-cache.h>
20 #define CACHE_COLOUR(vaddr)	((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
32  *	The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
38  *	See Documentation/core-api/cachetlb.rst for more information.
40  *	effects are cache-type (VIVT/VIPT/PIPT) specific.
45  *		Currently only needed for cache-v6.S and cache-v7.S, see
55  *             inner shareable and invalidate the I-cache.
68  *		- start - user start address (inclusive, page aligned)
69  *		- end   - user end address   (exclusive, page aligned)
70  *		- flags - vma->vm_flags field
75  *		region described by start, end.  If you have non-snooping
77  *		- start  - virtual start address
78  *		- end    - virtual end address
83  *		region described by start, end.  If you have non-snooping
85  *		- start  - virtual start address
86  *		- end    - virtual end address
91  *		- kaddr  - page address
92  *		- size   - region size
100  *		- start  - virtual start address
101  *		- end    - virtual end address
138  * These are private to the dma-mapping API.  Do not use directly.
157  * These are private to the dma-mapping API.  Do not use directly.
182 /* Invalidate I-cache */
187 /* Invalidate I-cache inner shareable */
193  * Optimized __flush_icache_all for the common cases. Note that UP ARMv7
230 	struct mm_struct *mm = vma->vm_mm;  in vivt_flush_cache_range()
234 					vma->vm_flags);  in vivt_flush_cache_range()
240 	struct mm_struct *mm = vma->vm_mm;  in vivt_flush_cache_page()
244 		__cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);  in vivt_flush_cache_page()
284  * cache page at virtual address page->virtual.
321 #define flush_dcache_mmap_lock(mapping)		xa_lock_irq(&mapping->i_pages)
322 #define flush_dcache_mmap_unlock(mapping)	xa_unlock_irq(&mapping->i_pages)
335  * vmalloc, ioremap etc) in kernel space for pages.  On non-VIPT
336  * caches, since the direct-mappings of these pages may contain cached
359  * Memory synchronization helpers for mixed cached vs non cached accesses.
373  * adjacent non-cached writer, each state variable must be located to
434  * Disabling cache access for one CPU in an ARMv7 SMP system is tricky.
437  * - Clear the SCTLR.C bit to prevent further cache allocations
438  * - Flush the desired level of cache
439  * - Clear the ACTLR "SMP" bit to disable local coherency
444  * WARNING -- After this has been called:
446  * - No ldrex/strex (and similar) instructions must be used.
447  * - The CPU is obviously no longer coherent with the other CPUs.
448  * - This is unlikely to work as expected if Linux is running non-secure.
452  * - This is known to apply to several ARMv7 processor implementations,
455  * - The clobber list is dictated by the call to v7_flush_dcache_*.
458  *   CONFIG_FRAME_POINTER=y.  ip is saved as well if ever r12-clobbering
459  *   trampoline are inserted by the linker and to keep sp 64-bit aligned.
463 	".arch	armv7-a \n\t" \