Lines Matching +full:0 +full:- +full:7
2 * TI DA850/OMAP-L138 chip specific setup
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
6 * Derived from: arch/arm/mach-davinci/da830.c
15 #include <linux/clk-provider.h>
21 #include <linux/mfd/da8xx-cfgchip.h>
22 #include <linux/platform_data/clk-da8xx-cfgchip.h>
23 #include <linux/platform_data/clk-davinci-pll.h>
24 #include <linux/platform_data/gpio-davinci.h>
41 #define DA850_PLL1_BASE 0x01e1a000
42 #define DA850_TIMER64P2_BASE 0x01f0c000
43 #define DA850_TIMER64P3_BASE 0x01f0d000
80 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
88 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
97 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
99 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
100 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
101 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
102 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
103 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
104 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
105 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
106 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
114 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
129 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
137 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
140 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
148 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
158 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
168 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
169 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
170 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
171 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
177 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
185 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
193 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
201 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
203 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
205 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
210 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
211 MUX_CFG(DA850, GPIO3_12, 7, 12, 15, 8, false)
212 MUX_CFG(DA850, GPIO3_13, 7, 8, 15, 8, false)
218 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
221 MUX_CFG(DA850, VPIF_DIN1, 15, 0, 15, 1, false)
229 MUX_CFG(DA850, VPIF_DIN9, 16, 0, 15, 1, false)
236 MUX_CFG(DA850, VPIF_CLKIN0, 14, 0, 15, 1, false)
242 MUX_CFG(DA850, VPIF_DOUT1, 17, 0, 15, 1, false)
250 MUX_CFG(DA850, VPIF_DOUT9, 18, 0, 15, 1, false)
264 -1
269 -1
278 -1
288 -1
298 -1
301 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
303 [IRQ_DA8XX_COMMTX] = 7,
304 [IRQ_DA8XX_COMMRX] = 7,
305 [IRQ_DA8XX_NINT] = 7,
306 [IRQ_DA8XX_EVTOUT0] = 7,
307 [IRQ_DA8XX_EVTOUT1] = 7,
308 [IRQ_DA8XX_EVTOUT2] = 7,
309 [IRQ_DA8XX_EVTOUT3] = 7,
310 [IRQ_DA8XX_EVTOUT4] = 7,
311 [IRQ_DA8XX_EVTOUT5] = 7,
312 [IRQ_DA8XX_EVTOUT6] = 7,
313 [IRQ_DA8XX_EVTOUT7] = 7,
314 [IRQ_DA8XX_CCINT0] = 7,
315 [IRQ_DA8XX_CCERRINT] = 7,
316 [IRQ_DA8XX_TCERRINT0] = 7,
317 [IRQ_DA8XX_AEMIFINT] = 7,
318 [IRQ_DA8XX_I2CINT0] = 7,
319 [IRQ_DA8XX_MMCSDINT0] = 7,
320 [IRQ_DA8XX_MMCSDINT1] = 7,
321 [IRQ_DA8XX_ALLINT0] = 7,
322 [IRQ_DA8XX_RTC] = 7,
323 [IRQ_DA8XX_SPINT0] = 7,
324 [IRQ_DA8XX_TINT12_0] = 7,
325 [IRQ_DA8XX_TINT34_0] = 7,
326 [IRQ_DA8XX_TINT12_1] = 7,
327 [IRQ_DA8XX_TINT34_1] = 7,
328 [IRQ_DA8XX_UARTINT0] = 7,
329 [IRQ_DA8XX_KEYMGRINT] = 7,
330 [IRQ_DA850_MPUADDRERR0] = 7,
331 [IRQ_DA8XX_CHIPINT0] = 7,
332 [IRQ_DA8XX_CHIPINT1] = 7,
333 [IRQ_DA8XX_CHIPINT2] = 7,
334 [IRQ_DA8XX_CHIPINT3] = 7,
335 [IRQ_DA8XX_TCERRINT1] = 7,
336 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
337 [IRQ_DA8XX_C0_RX_PULSE] = 7,
338 [IRQ_DA8XX_C0_TX_PULSE] = 7,
339 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
340 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
341 [IRQ_DA8XX_C1_RX_PULSE] = 7,
342 [IRQ_DA8XX_C1_TX_PULSE] = 7,
343 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
344 [IRQ_DA8XX_MEMERR] = 7,
345 [IRQ_DA8XX_GPIO0] = 7,
346 [IRQ_DA8XX_GPIO1] = 7,
347 [IRQ_DA8XX_GPIO2] = 7,
348 [IRQ_DA8XX_GPIO3] = 7,
349 [IRQ_DA8XX_GPIO4] = 7,
350 [IRQ_DA8XX_GPIO5] = 7,
351 [IRQ_DA8XX_GPIO6] = 7,
352 [IRQ_DA8XX_GPIO7] = 7,
353 [IRQ_DA8XX_GPIO8] = 7,
354 [IRQ_DA8XX_I2CINT1] = 7,
355 [IRQ_DA8XX_LCDINT] = 7,
356 [IRQ_DA8XX_UARTINT1] = 7,
357 [IRQ_DA8XX_MCASPINT] = 7,
358 [IRQ_DA8XX_ALLINT1] = 7,
359 [IRQ_DA8XX_SPINT1] = 7,
360 [IRQ_DA8XX_UHPI_INT1] = 7,
361 [IRQ_DA8XX_USB_INT] = 7,
362 [IRQ_DA8XX_IRQN] = 7,
363 [IRQ_DA8XX_RWAKEUP] = 7,
364 [IRQ_DA8XX_UARTINT2] = 7,
365 [IRQ_DA8XX_DFTSSINT] = 7,
366 [IRQ_DA8XX_EHRPWM0] = 7,
367 [IRQ_DA8XX_EHRPWM0TZ] = 7,
368 [IRQ_DA8XX_EHRPWM1] = 7,
369 [IRQ_DA8XX_EHRPWM1TZ] = 7,
370 [IRQ_DA850_SATAINT] = 7,
371 [IRQ_DA850_TINTALL_2] = 7,
372 [IRQ_DA8XX_ECAP0] = 7,
373 [IRQ_DA8XX_ECAP1] = 7,
374 [IRQ_DA8XX_ECAP2] = 7,
375 [IRQ_DA850_MMCSDINT0_1] = 7,
376 [IRQ_DA850_MMCSDINT1_1] = 7,
377 [IRQ_DA850_T12CMPINT0_2] = 7,
378 [IRQ_DA850_T12CMPINT1_2] = 7,
379 [IRQ_DA850_T12CMPINT2_2] = 7,
380 [IRQ_DA850_T12CMPINT3_2] = 7,
381 [IRQ_DA850_T12CMPINT4_2] = 7,
382 [IRQ_DA850_T12CMPINT5_2] = 7,
383 [IRQ_DA850_T12CMPINT6_2] = 7,
384 [IRQ_DA850_T12CMPINT7_2] = 7,
385 [IRQ_DA850_T12CMPINT0_3] = 7,
386 [IRQ_DA850_T12CMPINT1_3] = 7,
387 [IRQ_DA850_T12CMPINT2_3] = 7,
388 [IRQ_DA850_T12CMPINT3_3] = 7,
389 [IRQ_DA850_T12CMPINT4_3] = 7,
390 [IRQ_DA850_T12CMPINT5_3] = 7,
391 [IRQ_DA850_T12CMPINT6_3] = 7,
392 [IRQ_DA850_T12CMPINT7_3] = 7,
393 [IRQ_DA850_RPIINT] = 7,
394 [IRQ_DA850_VPIFINT] = 7,
395 [IRQ_DA850_CCINT1] = 7,
396 [IRQ_DA850_CCERRINT1] = 7,
397 [IRQ_DA850_TCERRINT2] = 7,
398 [IRQ_DA850_TINTALL_3] = 7,
399 [IRQ_DA850_MCBSP0RINT] = 7,
400 [IRQ_DA850_MCBSP0XINT] = 7,
401 [IRQ_DA850_MCBSP1RINT] = 7,
402 [IRQ_DA850_MCBSP1XINT] = 7,
403 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
424 .variant = 0x0,
425 .part_no = 0xb7d1,
426 .manufacturer = 0x017, /* 0x02f >> 1 */
428 .name = "da850/omap-l138",
431 .variant = 0x1,
432 .part_no = 0xb7d1,
433 .manufacturer = 0x017, /* 0x02f >> 1 */
435 .name = "da850/omap-l138/am18x",
463 * T0_BOT: Timer 0, bottom : Used for clock_event
464 * T0_TOP: Timer 0, top : Used for clocksource
558 .driver_data = 0,
584 return -ENODEV; in da850_set_voltage()
588 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); in da850_set_voltage()
599 return 0; in da850_regulator_init()
604 .name = "cpufreq-davinci",
608 .id = -1,
621 for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { in da850_register_cpufreq()
633 return 0; in da850_register_cpufreq()
643 .end = DA8XX_VPIF_BASE + 0xfff,
650 .id = -1,
669 .id = -1,
693 .id = -1,
736 .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
767 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); in da850_init_time()
782 .end = DA850_PLL1_BASE + SZ_4K - 1,
790 .name = "da850-pll1",
791 .id = -1,
802 .end = DA8XX_PSC0_BASE + SZ_4K - 1,
808 .name = "da850-psc0",
809 .id = -1,
817 .end = DA8XX_PSC1_BASE + SZ_4K - 1,
823 .name = "da850-psc1",
824 .id = -1,
832 .name = "da850-async1-clksrc",
833 .id = -1,
842 .name = "da850-async3-clksrc",
843 .id = -1,
852 .name = "da830-tbclksync",
853 .id = -1,