Lines Matching +full:1 +full:- +full:7
12 #include <linux/clk-provider.h>
15 #include <linux/dma-mapping.h>
19 #include <linux/platform_data/gpio-davinci.h>
38 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
61 .end = DM646X_EMAC_BASE + SZ_16K - 1,
88 .id = 1,
99 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
119 MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
121 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
123 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
125 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
150 [IRQ_DM646X_VP_VERTINT0] = 7,
151 [IRQ_DM646X_VP_VERTINT1] = 7,
152 [IRQ_DM646X_VP_VERTINT2] = 7,
153 [IRQ_DM646X_VP_VERTINT3] = 7,
154 [IRQ_DM646X_VP_ERRINT] = 7,
155 [IRQ_DM646X_RESERVED_1] = 7,
156 [IRQ_DM646X_RESERVED_2] = 7,
157 [IRQ_DM646X_WDINT] = 7,
158 [IRQ_DM646X_CRGENINT0] = 7,
159 [IRQ_DM646X_CRGENINT1] = 7,
160 [IRQ_DM646X_TSIFINT0] = 7,
161 [IRQ_DM646X_TSIFINT1] = 7,
162 [IRQ_DM646X_VDCEINT] = 7,
163 [IRQ_DM646X_USBINT] = 7,
164 [IRQ_DM646X_USBDMAINT] = 7,
165 [IRQ_DM646X_PCIINT] = 7,
166 [IRQ_CCINT0] = 7, /* dma */
167 [IRQ_CCERRINT] = 7, /* dma */
168 [IRQ_TCERRINT0] = 7, /* dma */
169 [IRQ_TCERRINT] = 7, /* dma */
170 [IRQ_DM646X_TCERRINT2] = 7,
171 [IRQ_DM646X_TCERRINT3] = 7,
172 [IRQ_DM646X_IDE] = 7,
173 [IRQ_DM646X_HPIINT] = 7,
174 [IRQ_DM646X_EMACRXTHINT] = 7,
175 [IRQ_DM646X_EMACRXINT] = 7,
176 [IRQ_DM646X_EMACTXINT] = 7,
177 [IRQ_DM646X_EMACMISCINT] = 7,
178 [IRQ_DM646X_MCASP0TXINT] = 7,
179 [IRQ_DM646X_MCASP0RXINT] = 7,
180 [IRQ_DM646X_RESERVED_3] = 7,
181 [IRQ_DM646X_MCASP1TXINT] = 7,
182 [IRQ_TINT0_TINT12] = 7, /* clockevent */
183 [IRQ_TINT0_TINT34] = 7, /* clocksource */
184 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
185 [IRQ_TINT1_TINT34] = 7, /* system tick */
186 [IRQ_PWMINT0] = 7,
187 [IRQ_PWMINT1] = 7,
188 [IRQ_DM646X_VLQINT] = 7,
189 [IRQ_I2C] = 7,
190 [IRQ_UARTINT0] = 7,
191 [IRQ_UARTINT1] = 7,
192 [IRQ_DM646X_UARTINT2] = 7,
193 [IRQ_DM646X_SPINT0] = 7,
194 [IRQ_DM646X_SPINT1] = 7,
195 [IRQ_DM646X_DSP2ARMINT] = 7,
196 [IRQ_DM646X_RESERVED_4] = 7,
197 [IRQ_DM646X_PSCINT] = 7,
198 [IRQ_DM646X_GPIO0] = 7,
199 [IRQ_DM646X_GPIO1] = 7,
200 [IRQ_DM646X_GPIO2] = 7,
201 [IRQ_DM646X_GPIO3] = 7,
202 [IRQ_DM646X_GPIO4] = 7,
203 [IRQ_DM646X_GPIO5] = 7,
204 [IRQ_DM646X_GPIO6] = 7,
205 [IRQ_DM646X_GPIO7] = 7,
206 [IRQ_DM646X_GPIOBNK0] = 7,
207 [IRQ_DM646X_GPIOBNK1] = 7,
208 [IRQ_DM646X_GPIOBNK2] = 7,
209 [IRQ_DM646X_DDRINT] = 7,
210 [IRQ_DM646X_AEMIFINT] = 7,
211 [IRQ_COMMTX] = 7,
212 [IRQ_COMMRX] = 7,
213 [IRQ_EMUINT] = 7,
216 /*----------------------------------------------------------------------*/
222 {1, 0},
224 {3, 1},
225 {-1, -1},
229 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
230 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
231 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
247 .end = 0x01c00000 + SZ_64K - 1,
253 .end = 0x01c10000 + SZ_1K - 1,
259 .end = 0x01c10400 + SZ_1K - 1,
265 .end = 0x01c10800 + SZ_1K - 1,
271 .end = 0x01c10c00 + SZ_1K - 1,
301 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
333 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
350 .name = "davinci-mcasp",
357 .name = "davinci-mcasp",
358 .id = 1,
364 .name = "spdif-dit",
365 .id = -1,
380 .id = -1,
404 .id = -1,
428 .id = -1,
440 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
470 /*----------------------------------------------------------------------*/
502 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
503 * T1_TOP: Timer 1, top : <unused>
673 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
679 .name = "dm646x-pll2",
680 .id = -1,