Lines Matching full:ip
56 ldr ip, CACHE_FLUSH
57 blx ip
66 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
67 bic ip, ip, #DDR2_SRPD_BIT
68 orr ip, ip, #DDR2_LPMODEN_BIT
69 str ip, [r0, #DDR2_SDRCR_OFFSET]
71 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
72 orr ip, ip, #DDR2_MCLKSTOPEN_BIT
73 str ip, [r0, #DDR2_SDRCR_OFFSET]
75 mov ip, #PHYRDY_CYCLES
76 1: subs ip, ip, #0x1
86 ldr ip, [r3, #PLLDIV1]
87 bic ip, ip, #PLLDIV_EN
88 str ip, [r3, #PLLDIV1]
91 ldr ip, [r3, #PLLCTL]
92 bic ip, ip, #PLLCTL_PLLENSRC
93 bic ip, ip, #PLLCTL_PLLEN
94 str ip, [r3, #PLLCTL]
97 mov ip, #PLL_BYPASS_CYCLES
98 2: subs ip, ip, #0x1
102 ldr ip, [r3, #PLLCTL]
103 orr ip, ip, #PLLCTL_PLLPWRDN
104 str ip, [r3, #PLLCTL]
107 ldr ip, [r4]
108 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
110 str ip, [r4]
115 ldr ip, [r4]
116 bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
117 str ip, [r4]
122 ldr ip, [r3, #PLLCTL]
123 bic ip, ip, #PLLCTL_PLLRST
124 str ip, [r3, #PLLCTL]
127 ldr ip, [r3, #PLLCTL]
128 bic ip, ip, #PLLCTL_PLLPWRDN
129 str ip, [r3, #PLLCTL]
131 mov ip, #PLL_RESET_CYCLES
132 3: subs ip, ip, #0x1
136 ldr ip, [r3, #PLLCTL]
137 orr ip, ip, #PLLCTL_PLLRST
138 str ip, [r3, #PLLCTL]
141 mov ip, #PLL_LOCK_CYCLES
142 4: subs ip, ip, #0x1
146 ldr ip, [r3, #PLLCTL]
147 bic ip, ip, #PLLCTL_PLLENSRC
148 orr ip, ip, #PLLCTL_PLLEN
149 str ip, [r3, #PLLCTL]
153 ldr ip, [r3, #PLLDIV1]
154 orr ip, ip, #PLLDIV_EN
155 str ip, [r3, #PLLDIV1]
167 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
168 bic ip, ip, #DDR2_MCLKSTOPEN_BIT
169 str ip, [r0, #DDR2_SDRCR_OFFSET]
171 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
172 bic ip, ip, #DDR2_LPMODEN_BIT
173 str ip, [r0, #DDR2_SDRCR_OFFSET]
191 ldr ip, [r1, r6]
192 bic ip, ip, #MDSTAT_STATE_MASK
193 orr ip, ip, r0
194 str ip, [r1, r6]
197 ldr ip, [r1, #PTCMD]
198 orr ip, ip, #0x1
199 str ip, [r1, #PTCMD]
203 ldr ip, [r1, #PTSTAT]
204 and ip, ip, #0x1
205 cmp ip, #0x0
212 ldr ip, [r1, r6]
213 and ip, ip, #MDSTAT_STATE_MASK
214 cmp ip, r0