Lines Matching full:rate
32 unsigned long rate; member
39 int (*set_rate)(struct clk *clk, unsigned long rate);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
51 .rate = EP93XX_EXT_CLK_RATE,
110 .rate = EP93XX_EXT_CLK_RATE,
114 .rate = EP93XX_EXT_CLK_RATE,
315 unsigned long rate = clk_get_rate(clk->parent); in get_uart_rate() local
320 return rate; in get_uart_rate()
322 return rate / 2; in get_uart_rate()
330 return clk->rate; in clk_get_rate()
334 static int set_keytchclk_rate(struct clk *clk, unsigned long rate) in set_keytchclk_rate() argument
344 * 1/4 or 1/16 the external clock rate depending on the in set_keytchclk_rate()
350 if (rate == EP93XX_KEYTCHCLK_DIV4) in set_keytchclk_rate()
352 else if (rate == EP93XX_KEYTCHCLK_DIV16) in set_keytchclk_rate()
358 clk->rate = rate; in set_keytchclk_rate()
362 static int calc_clk_div(struct clk *clk, unsigned long rate, in calc_clk_div() argument
369 /* Don't exceed the maximum rate */ in calc_clk_div()
370 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4); in calc_clk_div()
371 rate = min(rate, max_rate); in calc_clk_div()
389 mclk_rate = mclk->rate * 2; in calc_clk_div()
393 __div = mclk_rate / (rate * __pdiv); in calc_clk_div()
399 if (!found || abs(actual_rate - rate) < rate_err) { in calc_clk_div()
405 clk->rate = actual_rate; in calc_clk_div()
406 rate_err = abs(actual_rate - rate); in calc_clk_div()
418 static int set_div_rate(struct clk *clk, unsigned long rate) in set_div_rate() argument
423 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); in set_div_rate()
431 /* Set the new esel, psel, pdiv and div bits for the new clock rate */ in set_div_rate()
439 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) in set_i2s_sclk_rate() argument
443 if (rate == clk_i2s_mclk.rate / 2) in set_i2s_sclk_rate()
446 else if (rate == clk_i2s_mclk.rate / 4) in set_i2s_sclk_rate()
452 clk_i2s_sclk.rate = rate; in set_i2s_sclk_rate()
456 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) in set_i2s_lrclk_rate() argument
461 if (rate == clk_i2s_sclk.rate / 32) in set_i2s_lrclk_rate()
464 else if (rate == clk_i2s_sclk.rate / 64) in set_i2s_lrclk_rate()
467 else if (rate == clk_i2s_sclk.rate / 128) in set_i2s_lrclk_rate()
473 clk_i2s_lrclk.rate = rate; in set_i2s_lrclk_rate()
477 int clk_set_rate(struct clk *clk, unsigned long rate) in clk_set_rate() argument
480 return clk->set_rate(clk, rate); in clk_set_rate()
486 long clk_round_rate(struct clk *clk, unsigned long rate) in clk_round_rate() argument
512 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
516 unsigned long long rate; in calc_pll_rate() local
519 rate = clk_xtali.rate; in calc_pll_rate()
520 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ in calc_pll_rate()
521 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ in calc_pll_rate()
522 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ in calc_pll_rate()
524 rate >>= 1; in calc_pll_rate()
526 return (unsigned long)rate; in calc_pll_rate()
531 clk_m2p0.rate = clk_h.rate; in ep93xx_dma_clock_init()
532 clk_m2p1.rate = clk_h.rate; in ep93xx_dma_clock_init()
533 clk_m2p2.rate = clk_h.rate; in ep93xx_dma_clock_init()
534 clk_m2p3.rate = clk_h.rate; in ep93xx_dma_clock_init()
535 clk_m2p4.rate = clk_h.rate; in ep93xx_dma_clock_init()
536 clk_m2p5.rate = clk_h.rate; in ep93xx_dma_clock_init()
537 clk_m2p6.rate = clk_h.rate; in ep93xx_dma_clock_init()
538 clk_m2p7.rate = clk_h.rate; in ep93xx_dma_clock_init()
539 clk_m2p8.rate = clk_h.rate; in ep93xx_dma_clock_init()
540 clk_m2p9.rate = clk_h.rate; in ep93xx_dma_clock_init()
541 clk_m2m0.rate = clk_h.rate; in ep93xx_dma_clock_init()
542 clk_m2m1.rate = clk_h.rate; in ep93xx_dma_clock_init()
549 /* Determine the bootloader configured pll1 rate */ in ep93xx_clock_init()
552 clk_pll1.rate = clk_xtali.rate; in ep93xx_clock_init()
554 clk_pll1.rate = calc_pll_rate(value); in ep93xx_clock_init()
557 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; in ep93xx_clock_init()
558 clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; in ep93xx_clock_init()
559 clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; in ep93xx_clock_init()
562 /* Determine the bootloader configured pll2 rate */ in ep93xx_clock_init()
565 clk_pll2.rate = clk_xtali.rate; in ep93xx_clock_init()
567 clk_pll2.rate = calc_pll_rate(value); in ep93xx_clock_init()
569 clk_pll2.rate = 0; in ep93xx_clock_init()
572 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1); in ep93xx_clock_init()
575 * EP93xx SSP clock rate was doubled in version E2. For more information in ep93xx_clock_init()
580 clk_spi.rate /= 2; in ep93xx_clock_init()
583 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000); in ep93xx_clock_init()
585 clk_f.rate / 1000000, clk_h.rate / 1000000, in ep93xx_clock_init()
586 clk_p.rate / 1000000); in ep93xx_clock_init()