20 static u32 used_sram_bitmap[4]; /* 128 16-dword pages */
36 		int bit;  in qmgr_set_irq()  local
38 		reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */  in qmgr_set_irq()
39 		bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */  in qmgr_set_irq()
40 		__raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit),  in qmgr_set_irq()
43 		/* IRQ source for queues 32-63 is fixed */  in qmgr_set_irq()
57 	/* ACK - it may clear any bits so don't rely on it */  in qmgr_irq1_a0()
58 	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]);  in qmgr_irq1_a0()
60 	en_bitmap = qmgr_regs->irqen[0];  in qmgr_irq1_a0()
63 		en_bitmap &= ~BIT(i);  in qmgr_irq1_a0()
64 		src = qmgr_regs->irqsrc[i >> 3];  in qmgr_irq1_a0()
65 		stat = qmgr_regs->stat1[i >> 3];  in qmgr_irq1_a0()
68 		if (stat & BIT(src & 3)) {  in qmgr_irq1_a0()
82 	/* ACK - it may clear any bits so don't rely on it */  in qmgr_irq2_a0()
83 	__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]);  in qmgr_irq2_a0()
85 	req_bitmap = qmgr_regs->irqen[1] & qmgr_regs->statne_h;  in qmgr_irq2_a0()
88 		req_bitmap &= ~BIT(i);  in qmgr_irq2_a0()
98 	int i, half = (irq == IRQ_IXP4XX_QM1 ? 0 : 1);  in qmgr_irq()  local
99 	u32 req_bitmap = __raw_readl(&qmgr_regs->irqstat[half]);  in qmgr_irq()
103 	__raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */  in qmgr_irq()
107 		req_bitmap &= ~BIT(i);  in qmgr_irq()
108 		i += half * HALF_QUEUES;  in qmgr_irq()
118 	int half = queue / 32;  in qmgr_enable_irq()  local
119 	u32 mask = 1 << (queue & (HALF_QUEUES - 1));  in qmgr_enable_irq()
122 	__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask,  in qmgr_enable_irq()
123 		     &qmgr_regs->irqen[half]);  in qmgr_enable_irq()
130 	int half = queue / 32;  in qmgr_disable_irq()  local
131 	u32 mask = 1 << (queue & (HALF_QUEUES - 1));  in qmgr_disable_irq()
134 	__raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask,  in qmgr_disable_irq()
135 		     &qmgr_regs->irqen[half]);  in qmgr_disable_irq()
136 	__raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */  in qmgr_disable_irq()
159 	u32 cfg, addr = 0, mask[4]; /* in 16-dwords */  in qmgr_request_queue()
165 		return -EINVAL;  in qmgr_request_queue()
185 		return -EINVAL;  in qmgr_request_queue()
190 	len /= 16;		/* in 16-dwords: 1, 2, 4 or 8 */  in qmgr_request_queue()
194 		return -ENODEV;  in qmgr_request_queue()
197 	if (__raw_readl(&qmgr_regs->sram[queue])) {  in qmgr_request_queue()
198 		err = -EBUSY;  in qmgr_request_queue()
211 		if (addr + len > ARRAY_SIZE(qmgr_regs->sram)) {  in qmgr_request_queue()
214 			err = -ENOMEM;  in qmgr_request_queue()
223 	__raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);  in qmgr_request_queue()
246 	cfg = __raw_readl(&qmgr_regs->sram[queue]);  in qmgr_release_queue()
260 	while (addr--)  in qmgr_release_queue()
273 	__raw_writel(0, &qmgr_regs->sram[queue]);  in qmgr_release_queue()
294 		return -EBUSY;  in qmgr_init()
298 		__raw_writel(0x33333333, &qmgr_regs->stat1[i]);  in qmgr_init()
299 		__raw_writel(0, &qmgr_regs->irqsrc[i]);  in qmgr_init()
302 		__raw_writel(0, &qmgr_regs->stat2[i]);  in qmgr_init()
303 		__raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[i]); /* clear */  in qmgr_init()
304 		__raw_writel(0, &qmgr_regs->irqen[i]);  in qmgr_init()
307 	__raw_writel(0xFFFFFFFF, &qmgr_regs->statne_h);  in qmgr_init()
308 	__raw_writel(0, &qmgr_regs->statf_h);  in qmgr_init()
311 		__raw_writel(0, &qmgr_regs->sram[i]);  in qmgr_init()