Lines Matching +full:0 +full:xd4000000
18 #define APB_PHYS_BASE 0xd4000000
19 #define APB_VIRT_BASE IOMEM(0xfe000000)
20 #define APB_PHYS_SIZE 0x00200000
22 #define AXI_PHYS_BASE 0xd4200000
23 #define AXI_VIRT_BASE IOMEM(0xfe200000)
24 #define AXI_PHYS_SIZE 0x00200000
26 /* Static Memory Controller - Chip Select 0 and 1 */
27 #define SMC_CS0_PHYS_BASE 0x80000000
28 #define SMC_CS0_PHYS_SIZE 0x10000000
29 #define SMC_CS1_PHYS_BASE 0x90000000
30 #define SMC_CS1_PHYS_SIZE 0x10000000
32 #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800)
35 #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000)
38 #define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000)
41 #define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00)