Lines Matching +full:0 +full:xff000
24 #define NETX_OFS_SYSTEM 0x00000
25 #define NETX_OFS_MEMCR 0x00100
26 #define NETX_OFS_DPMAS 0x03000
27 #define NETX_OFS_GPIO 0x00800
28 #define NETX_OFS_PIO 0x00900
29 #define NETX_OFS_UART0 0x00a00
30 #define NETX_OFS_UART1 0x00a40
31 #define NETX_OFS_UART2 0x00a80
32 #define NETX_OF_MIIMU 0x00b00
33 #define NETX_OFS_SPI 0x00c00
34 #define NETX_OFS_I2C 0x00d00
35 #define NETX_OFS_SYSTIME 0x01100
36 #define NETX_OFS_RTC 0x01200
37 #define NETX_OFS_EXTBUS 0x03600
38 #define NETX_OFS_LCD 0x04000
39 #define NETX_OFS_USB 0x20000
40 #define NETX_OFS_XMAC0 0x60000
41 #define NETX_OFS_XMAC1 0x61000
42 #define NETX_OFS_XMAC2 0x62000
43 #define NETX_OFS_XMAC3 0x63000
44 #define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000)
45 #define NETX_OFS_PFIFO 0x64000
46 #define NETX_OFS_XPEC0 0x70000
47 #define NETX_OFS_XPEC1 0x74000
48 #define NETX_OFS_XPEC2 0x78000
49 #define NETX_OFS_XPEC3 0x7c000
50 #define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000)
51 #define NETX_OFS_VIC 0xff000
119 #define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00)
120 #define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04)
121 #define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
124 /* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */
125 #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c)
127 #define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
128 #define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
129 #define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70)
130 #define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200)
131 #define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204)
132 #define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208)
133 #define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c)
136 #define NETX_SYSTEM_RES_CR_RSTIN (1<<0)
163 #define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13)
168 #define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4)
169 #define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf)
171 #define PHY_MODE_10BASE_T_HALF 0
189 #define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2))
190 #define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2))
191 #define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2))
192 #define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2))
193 #define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2))
194 #define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc)
195 #define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0)
196 #define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4)
197 #define NETX_GPIO_LINE NETX_GPIO_REG(0xc8)
198 #define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0)
201 #define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0)
202 #define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1)
203 #define NETX_GPIO_CFG_IOCFG_GP_UART (0x2)
205 #define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3)
209 #define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5)
216 #define NETX_GPIO_COUNTER_CTRL_RUN (1<<0)
234 #define NETX_PIO_INPIO NETX_PIO_REG(0x0)
235 #define NETX_PIO_OUTPIO NETX_PIO_REG(0x4)
236 #define NETX_PIO_OEPIO NETX_PIO_REG(0x8)
246 #define MIIMU_SNRDY (1<<0)
252 #define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6)
253 #define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11)
254 #define MIIMU_DATA(data) (((data) & 0xffff) << 16)
261 #define NETX_XPEC_R0_OFS 0x00
262 #define NETX_XPEC_R1_OFS 0x04
263 #define NETX_XPEC_R2_OFS 0x08
264 #define NETX_XPEC_R3_OFS 0x0c
265 #define NETX_XPEC_R4_OFS 0x10
266 #define NETX_XPEC_R5_OFS 0x14
267 #define NETX_XPEC_R6_OFS 0x18
268 #define NETX_XPEC_R7_OFS 0x1c
269 #define NETX_XPEC_RANGE01_OFS 0x20
270 #define NETX_XPEC_RANGE23_OFS 0x24
271 #define NETX_XPEC_RANGE45_OFS 0x28
272 #define NETX_XPEC_RANGE67_OFS 0x2c
273 #define NETX_XPEC_PC_OFS 0x48
274 #define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2))
275 #define NETX_XPEC_IRQ_OFS 0x8c
276 #define NETX_XPEC_SYSTIME_NS_OFS 0x90
277 #define NETX_XPEC_FIFO_DATA_OFS 0x94
278 #define NETX_XPEC_SYSTIME_S_OFS 0x98
279 #define NETX_XPEC_ADC_OFS 0x9c
280 #define NETX_XPEC_URX_COUNT_OFS 0x40
281 #define NETX_XPEC_UTX_COUNT_OFS 0x44
282 #define NETX_XPEC_PC_OFS 0x48
283 #define NETX_XPEC_ZERO_OFS 0x4c
284 #define NETX_XPEC_STATCFG_OFS 0x50
285 #define NETX_XPEC_EC_MASKA_OFS 0x54
286 #define NETX_XPEC_EC_MASKB_OFS 0x58
287 #define NETX_XPEC_EC_MASK0_OFS 0x5c
288 #define NETX_XPEC_EC_MASK8_OFS 0x7c
289 #define NETX_XPEC_EC_MASK9_OFS 0x80
290 #define NETX_XPEC_XPU_HOLD_PC_OFS 0x100
291 #define NETX_XPEC_RAM_START_OFS 0x2000
294 #define XPU_HOLD_PC (1<<0)
297 #define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000
298 #define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff
299 #define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400
300 #define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff
301 #define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00
302 #define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04
303 #define NETX_XMAC_STATUS_SHARED0_OFS 0x840
304 #define NETX_XMAC_CONFIG_SHARED0_OFS 0x844
305 #define NETX_XMAC_STATUS_SHARED1_OFS 0x848
306 #define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c
307 #define NETX_XMAC_STATUS_SHARED2_OFS 0x850
308 #define NETX_XMAC_CONFIG_SHARED2_OFS 0x854
309 #define NETX_XMAC_STATUS_SHARED3_OFS 0x858
310 #define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c
321 #define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2))
322 #define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2))
323 #define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100)
324 #define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104)
325 #define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108)
326 #define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c)
327 #define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110)
328 #define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2))
329 #define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2))
338 #define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */
339 #define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40)
340 #define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44)
341 #define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48)
342 #define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c)
343 #define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80)
344 #define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84)
347 #define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24)
348 #define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16)
349 #define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8)
350 #define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0)
359 #define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8)
360 #define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0)
361 #define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0)
362 #define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608)
363 #define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c)
364 #define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs))
365 #define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */
366 #define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624)
367 #define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628)
368 #define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */
369 #define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634)
370 #define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638)
382 #define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28)
397 #define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29)
398 #define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26)
399 #define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23)
400 #define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20)
401 #define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17)
402 #define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12)
403 #define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7)
410 #define NETX_EXT_CONFIG_CS_ENABLE (1<<0)
420 #define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30)
429 #define NETX_I2C_CTRL NETX_I2C_REG(0x0)
430 #define NETX_I2C_DATA NETX_I2C_REG(0x4)