Lines Matching +full:0 +full:xe8000000
26 #define H2P2_DBG_FPGA_BASE 0xE8000000 /* VA */
28 #define H2P2_DBG_FPGA_START 0x04000000 /* PA */
30 #define H2P2_DBG_FPGA_ETHR_START (H2P2_DBG_FPGA_START + 0x300)
31 #define H2P2_DBG_FPGA_FPGA_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x10) /* FPGA Revision */
32 #define H2P2_DBG_FPGA_BOARD_REV IOMEM(H2P2_DBG_FPGA_BASE + 0x12) /* Board Revision */
33 #define H2P2_DBG_FPGA_GPIO IOMEM(H2P2_DBG_FPGA_BASE + 0x14) /* GPIO outputs */
34 #define H2P2_DBG_FPGA_LEDS IOMEM(H2P2_DBG_FPGA_BASE + 0x16) /* LEDs outputs */
35 #define H2P2_DBG_FPGA_MISC_INPUTS IOMEM(H2P2_DBG_FPGA_BASE + 0x18) /* Misc inputs */
36 #define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
37 #define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
45 #define H2P2_DBG_FPGA_LOAD_METER (1 << 0) // A bit of fun on our board ...
49 #define H2P2_DBG_FPGA_P2_LED_TIMER (1 << 0)