2  * OMAP MPUSS low power code
7  * OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
10  * CPU0, CPU1 and MPUSS each have there own power domain and
11  * hence multiple low power combinations of MPUSS are possible.
16  * to the Cortex-A9 processor must be asserted by the external
17  * power controller.
20  * below modes are supported from power gain vs latency point of view.
23  *	----------------------------------------------
29  *	----------------------------------------------
32  * and first to wake-up when MPUSS low power states are excercised
52 #include <asm/hardware/cache-l2x0.h>
57 #include "omap4-sar-layout.h"
64 #include "prm-regbits-44xx.h"
79  * struct cpu_pm_ops - CPU pm operations
85  * Structure holds functions pointer for CPU low power operations like
126 	if (pm_info->wkup_sar_addr)  in set_cpu_wakeup_addr()
127 		writel_relaxed(addr, pm_info->wkup_sar_addr);  in set_cpu_wakeup_addr()
131  * Store the SCU power status value to scratchpad memory
152 	if (pm_info->scu_sar_addr)  in scu_pwrst_prepare()
153 		writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);  in scu_pwrst_prepare()
185  * Store the CPU cluster state for L2X0 low power operations.
191 	if (pm_info->l2x0_sar_addr)  in l2x0_pwrst_prepare()
192 		writel_relaxed(save_state, pm_info->l2x0_sar_addr);  in l2x0_pwrst_prepare()
217  * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
218  * The purpose of this function is to manage low power programming
221  * @power_state: Low power state.
225  *	0 - Nothing lost and no need to save: MPUSS INACTIVE
226  *	1 - CPUx L1 and logic lost: MPUSS CSWR
227  *	2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
228  *	3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
237 		return -ENXIO;  in omap4_enter_lowpower()
260 		return -ENXIO;  in omap4_enter_lowpower()
275 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);  in omap4_enter_lowpower()
276 	pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);  in omap4_enter_lowpower()
282 	 * Call low level function  with targeted low power state.  in omap4_enter_lowpower()
293 	 * Restore the CPUx power state to ON otherwise CPUx  in omap4_enter_lowpower()
294 	 * power domain can transitions to programmed low power  in omap4_enter_lowpower()
295 	 * state while doing WFI outside the low powe code. On  in omap4_enter_lowpower()
300 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_enter_lowpower()
310  * @power_state: CPU low power state.
318 		return -ENXIO;  in omap4_hotplug_cpu()
320 	/* Use the achievable power state for the domain */  in omap4_hotplug_cpu()
321 	power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,  in omap4_hotplug_cpu()
327 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_hotplug_cpu()
328 	pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);  in omap4_hotplug_cpu()
333 	 * CPU never retuns back if targeted power state is OFF mode.  in omap4_hotplug_cpu()
339 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_hotplug_cpu()
367 		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");  in omap4_mpuss_init()
368 		return -ENODEV;  in omap4_mpuss_init()
374 		pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;  in omap4_mpuss_init()
376 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
379 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
381 		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;  in omap4_mpuss_init()
383 	pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");  in omap4_mpuss_init()
384 	if (!pm_info->pwrdm) {  in omap4_mpuss_init()
386 		return -ENODEV;  in omap4_mpuss_init()
389 	/* Clear CPU previous power domain state */  in omap4_mpuss_init()
390 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_mpuss_init()
393 	/* Initialise CPU0 power domain state to ON */  in omap4_mpuss_init()
394 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_mpuss_init()
398 		pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;  in omap4_mpuss_init()
400 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
403 			pm_info->wkup_sar_addr = sar_base +  in omap4_mpuss_init()
405 		pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;  in omap4_mpuss_init()
408 	pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");  in omap4_mpuss_init()
409 	if (!pm_info->pwrdm) {  in omap4_mpuss_init()
411 		return -ENODEV;  in omap4_mpuss_init()
414 	/* Clear CPU previous power domain state */  in omap4_mpuss_init()
415 	pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);  in omap4_mpuss_init()
418 	/* Initialise CPU1 power domain state to ON */  in omap4_mpuss_init()
419 	pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);  in omap4_mpuss_init()
423 		pr_err("Failed to lookup MPUSS power domain\n");  in omap4_mpuss_init()
424 		return -ENODEV;  in omap4_mpuss_init()
430 		/* Save device type on scratchpad for low level code to use */  in omap4_mpuss_init()