Lines Matching full:cpu1
154 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device. in omap4_secondary_init()
156 * init and for CPU1, a secure PPA API provided. CPU0 must be ON in omap4_secondary_init()
157 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+. in omap4_secondary_init()
218 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to in omap4_boot_secondary()
223 * 4.3.4.2 Power States of CPU0 and CPU1 in omap4_boot_secondary()
233 * Because the ROM Code is based on the r1pX GIC, the CPU1 in omap4_boot_secondary()
236 * 1) Before doing the CPU1 wakeup, CPU0 must disable in omap4_boot_secondary()
238 * 2) CPU1 must re-enable the GIC distributor on in omap4_boot_secondary()
325 * We may need to reset CPU1 before configuring, otherwise kexec boot can end
327 * occasionally fail to bring up CPU1 on 4430 if CPU1 fails to enter deeper
343 pr_warn("smp: CPU1 not parked?\n"); in omap4_smp_maybe_reset_cpu1()
356 * If omap4 or 5 has NS_PA_ADDR configured, CPU1 may be in a in omap4_smp_maybe_reset_cpu1()
370 pr_info("smp: CPU1 parked within kernel, needs reset (0x%lx 0x%lx)\n", in omap4_smp_maybe_reset_cpu1()