Lines Matching +full:0 +full:x00020003
49 memblock_add(0xa0000000, SZ_128M); in eseries_fixup()
51 memblock_add(0xa0000000, SZ_64M); in eseries_fixup()
76 gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); in eseries_tmio_enable()
77 gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); in eseries_tmio_enable()
83 return 0; in eseries_tmio_enable()
88 gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); in eseries_tmio_disable()
89 gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); in eseries_tmio_disable()
90 return 0; in eseries_tmio_disable()
95 gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); in eseries_tmio_suspend()
96 return 0; in eseries_tmio_suspend()
103 return 0; in eseries_tmio_resume()
110 gpio_direction_output(GPIO_ESERIES_TMIO_SUSPEND, 0); in eseries_get_tmio_gpios()
111 gpio_direction_output(GPIO_ESERIES_TMIO_PCLR, 0); in eseries_get_tmio_gpios()
116 [0] = {
118 .end = PXA_CS4_PHYS + 0x1fffff,
131 clk_register_fixed_rate(NULL, "CLK_CK32K", NULL, 0, 32768); in eseries_register_clks()
173 .atag_offset = 0x100,
224 .atag_offset = 0x100,
250 .sync = 0,
257 .lccr3 = 0,
288 .offset = 0,
292 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
295 .options = 0,
348 .atag_offset = 0x100,
364 .lcd_format = 0x00008023,
365 .lcdd_cntl1 = 0x0f000000,
366 .lcdd_cntl2 = 0x0003ffff,
367 .genlcd_cntl1 = 0x00ffff03,
368 .genlcd_cntl2 = 0x003c0f03,
369 .genlcd_cntl3 = 0x000143aa,
379 .crtc_ss = 0x80140013,
380 .crtc_ls = 0x81150110,
381 .crtc_gs = 0x80050005,
382 .crtc_vpos_gs = 0x000a0009,
383 .crtc_rev = 0x0040010a,
384 .crtc_dclk = 0xa906000a,
385 .crtc_gclk = 0x80050108,
386 .crtc_goe = 0x80050108,
393 .crtc_ps1_active = 0x41060010,
397 .init_data1 = 0x21002103,
398 .gpio_dir1 = 0xffffdeff,
399 .gpio_oe1 = 0x03c00643,
400 .init_data2 = 0x003f003f,
401 .gpio_dir2 = 0xffffffff,
402 .gpio_oe2 = 0x000000ff,
415 [0] = {
416 .start = 0x0c000000,
417 .end = 0x0cffffff,
544 .atag_offset = 0x100,
560 .lcd_format = 0x00008003,
561 .lcdd_cntl1 = 0x00000000,
562 .lcdd_cntl2 = 0x0003ffff,
563 .genlcd_cntl1 = 0x00fff003,
564 .genlcd_cntl2 = 0x003c0f03,
565 .genlcd_cntl3 = 0x000143aa,
575 .crtc_ss = 0x80150014,
576 .crtc_ls = 0x8014000d,
577 .crtc_gs = 0xc1000005,
578 .crtc_vpos_gs = 0x00020147,
579 .crtc_rev = 0x0040010a,
580 .crtc_dclk = 0xa1700030,
581 .crtc_gclk = 0x80cc0015,
582 .crtc_goe = 0x80cc0015,
583 .crtc_ps1_active = 0x61060017,
593 .init_data1 = 0x01192f1b,
594 .gpio_dir1 = 0xd5ffdeff,
595 .gpio_oe1 = 0x000020bf,
596 .init_data2 = 0x010f010f,
597 .gpio_dir2 = 0xffffffff,
598 .gpio_oe2 = 0x000001cf,
611 [0] = {
612 .start = 0x0c000000,
613 .end = 0x0cffffff,
694 .scr_pll2cr = 0x0cc1,
695 .scr_gper = 0,
743 .atag_offset = 0x100,
770 .lcd_format = 0x00008003,
771 .lcdd_cntl1 = 0x02a00000,
772 .lcdd_cntl2 = 0x0003ffff,
773 .genlcd_cntl1 = 0x000ff2a3,
774 .genlcd_cntl2 = 0x000002a3,
775 .genlcd_cntl3 = 0x000102aa,
779 [0] = {
786 .crtc_ss = 0x80350034,
787 .crtc_ls = 0x802b0026,
788 .crtc_gs = 0x80160016,
789 .crtc_vpos_gs = 0x00020003,
790 .crtc_rev = 0x0040001d,
791 .crtc_dclk = 0xe0000000,
792 .crtc_gclk = 0x82a50049,
793 .crtc_goe = 0x80ee001c,
794 .crtc_ps1_active = 0x00000000,
799 .sysclk_divider = 0,
807 .upper_margin = 0,
809 .crtc_ss = 0xd010000f,
810 .crtc_ls = 0x80070003,
811 .crtc_gs = 0x80000000,
812 .crtc_vpos_gs = 0x01460147,
813 .crtc_rev = 0x00400003,
814 .crtc_dclk = 0xa1700030,
815 .crtc_gclk = 0x814b0008,
816 .crtc_goe = 0x80cc0015,
817 .crtc_ps1_active = 0x00000000,
822 .sysclk_divider = 0,
829 .init_data1 = 0xc13fc019,
830 .gpio_dir1 = 0x3e40df7f,
831 .gpio_oe1 = 0x003c3000,
832 .init_data2 = 0x00000000,
833 .gpio_dir2 = 0x00000000,
834 .gpio_oe2 = 0x00000000,
838 .ext_cntl = 0x09640011,
839 .sdram_mode_reg = 0x00600021,
840 .ext_timing_cntl = 0x10001545,
841 .io_cntl = 0x7ddd7333,
842 .size = 0x1fffff,
851 tmp |= 0x100; in e800_tg_change()
853 tmp &= ~0x100; in e800_tg_change()
872 [0] = {
873 .start = 0x0c000000,
874 .end = 0x0cffffff,
910 .scr_pll2cr = 0x0cc1,
911 .scr_gper = 0,
958 .atag_offset = 0x100,