61 	 * Synchronise with the boot thread.  in qcom_secondary_init()
72 	node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");  in scss_release_secondary()
75 		return -ENXIO;  in scss_release_secondary()
81 		return -ENOMEM;  in scss_release_secondary()
95 	void __iomem *reg, *saw_reg;  in kpssv1_release_secondary()  local
101 		return -ENODEV;  in kpssv1_release_secondary()
105 		ret = -ENODEV;  in kpssv1_release_secondary()
111 		ret = -ENODEV;  in kpssv1_release_secondary()
115 	reg = of_iomap(acc_node, 0);  in kpssv1_release_secondary()
116 	if (!reg) {  in kpssv1_release_secondary()
117 		ret = -ENOMEM;  in kpssv1_release_secondary()
123 		ret = -ENOMEM;  in kpssv1_release_secondary()
132 	/* Krait bring-up sequence */  in kpssv1_release_secondary()
134 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
136 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
141 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
146 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
151 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
156 	writel_relaxed(val, reg + APCS_CPU_PWR_CTL);  in kpssv1_release_secondary()
161 	iounmap(reg);  in kpssv1_release_secondary()
173 	void __iomem *reg;  in kpssv2_release_secondary()  local
181 		return -ENODEV;  in kpssv2_release_secondary()
185 		ret = -ENODEV;  in kpssv2_release_secondary()
189 	l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);  in kpssv2_release_secondary()
191 		ret = -ENODEV;  in kpssv2_release_secondary()
197 		ret = -ENODEV;  in kpssv2_release_secondary()
201 	reg = of_iomap(acc_node, 0);  in kpssv2_release_secondary()
202 	if (!reg) {  in kpssv2_release_secondary()
203 		ret = -ENOMEM;  in kpssv2_release_secondary()
209 		ret = -ENOMEM;  in kpssv2_release_secondary()
215 	writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);  in kpssv2_release_secondary()
222 	writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);  in kpssv2_release_secondary()
229 	writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);  in kpssv2_release_secondary()
237 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
242 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
247 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
251 	writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);  in kpssv2_release_secondary()
258 	iounmap(reg);  in kpssv2_release_secondary()
284 	 * set synchronisation state between this boot processor  in qcom_boot_secondary()
285 	 * and the secondary one  in qcom_boot_secondary()
290 	 * Send the secondary CPU a soft interrupt, thereby causing  in qcom_boot_secondary()
291 	 * the boot monitor to read the system wide flags register,  in qcom_boot_secondary()
297 	 * now the secondary core is starting up let it run its  in qcom_boot_secondary()
331 		pr_warn("Failed to set CPU boot address, disabling SMP\n");  in qcom_smp_prepare_cpus()
343 CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
353 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
363 CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);