Lines Matching +full:s3c6400 +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/dma-mapping.h>
30 #include <linux/irqchip/arm-vic.h>
40 #include <mach/regs-gpio.h>
41 #include <mach/gpio-samsung.h>
46 #include <plat/gpio-cfg.h>
47 #include <plat/pwm-core.h>
48 #include <plat/regs-irqtype.h>
51 #include "irq-uart.h"
52 #include "watchdog-reset.h"
68 /* uart registration process */
72 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no); in s3c64xx_init_uarts()
77 static const char name_s3c6400[] = "S3C6400";
100 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
158 .name = "s3c64xx-core",
159 .dev_name = "s3c64xx-core",
175 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; in samsung_set_timer_source()
222 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
223 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
224 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
225 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
226 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
227 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
246 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
254 mask |= (u32)data->chip_data; in s3c_irq_eint_mask()
263 mask &= ~((u32)data->chip_data); in s3c_irq_eint_unmask()
269 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND); in s3c_irq_eint_ack()
274 /* compiler should in-line these */ in s3c_irq_eint_maskack()
281 int offs = eint_offset(data->irq); in s3c_irq_eint_set_type()
289 return -EINVAL; in s3c_irq_eint_set_type()
323 return -1; in s3c_irq_eint_set_type()
329 shift = ((offs - 16) / 2) * 4; in s3c_irq_eint_set_type()
343 pin = S3C64XX_GPL(offs + 8 - 16); in s3c_irq_eint_set_type()
346 pin = S3C64XX_GPM(offs - 23); in s3c_irq_eint_set_type()
356 .name = "s3c-eint",
379 status &= (1 << (end - start + 1)) - 1; in s3c_irq_demux_eint()
413 /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */ in s3c64xx_init_irq_eint()
415 return -ENODEV; in s3c64xx_init_irq_eint()