Lines Matching +full:non +full:- +full:prefetchable
2 * linux/arch/arm/mach-sa1100/pci-nanoengine.c
6 * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <asm/mach-types.h>
35 if (bus->number != 0 || (devfn >> 3) != 0) in nanoengine_pci_map_bus()
39 ((bus->number << 16) | (devfn << 8) | (where & ~3)); in nanoengine_pci_map_bus()
58 .name = "PCI non-prefetchable",
62 .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
63 /* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/
68 * nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it
76 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
77 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
78 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
79 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
85 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
86 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
87 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
88 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
89 pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
90 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
92 * On the other hand, if we do not request the prefetchable memory resource,
93 * linux will alloc it first and the two non-prefetchable memory areas that
102 pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff]
103 pci 0000:00:00.0: reg 14: [io 0x0000-0x003f]
104 pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff]
105 pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref]
110 pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref]
111 pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff]
112 pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff])
113 pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff]
114 pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff])
115 pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f]
116 pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f])
118 # lspci -vv -s 0000:00:00.0
120 …Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisIN…
121 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ I…
124 Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K]
126 Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K]
129 Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-)
130 Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME-
136 .name = "PCI prefetchable",
138 .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
146 return -EBUSY; in pci_nanoengine_setup_resources()
150 printk(KERN_ERR "PCI: unable to allocate non prefetchable\n"); in pci_nanoengine_setup_resources()
151 return -EBUSY; in pci_nanoengine_setup_resources()
156 printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); in pci_nanoengine_setup_resources()
157 return -EBUSY; in pci_nanoengine_setup_resources()
159 pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset); in pci_nanoengine_setup_resources()
160 pci_add_resource_offset(&sys->resources, in pci_nanoengine_setup_resources()
161 &pci_non_prefetchable_memory, sys->mem_offset); in pci_nanoengine_setup_resources()
162 pci_add_resource_offset(&sys->resources, in pci_nanoengine_setup_resources()
163 &pci_prefetchable_memory, sys->mem_offset); in pci_nanoengine_setup_resources()
176 sys->mem_offset = NANO_PCI_MEM_RW_PHYS; in pci_nanoengine_setup()
177 sys->io_offset = 0x400; in pci_nanoengine_setup()