39 static void tegra_secondary_init(unsigned int cpu)  in tegra_secondary_init()  argument
41 	cpumask_set_cpu(cpu, &tegra_cpu_init_mask);  in tegra_secondary_init()
45 static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)  in tegra20_boot_secondary()  argument
47 	cpu = cpu_logical_map(cpu);  in tegra20_boot_secondary()
50 	 * Force the CPU into reset. The CPU must remain in reset when  in tegra20_boot_secondary()
52 	 * flow controller to stop driving reset if the CPU has been  in tegra20_boot_secondary()
54 	 * effect on first boot of the CPU since it should already be  in tegra20_boot_secondary()
57 	tegra_put_cpu_in_reset(cpu);  in tegra20_boot_secondary()
60 	 * Unhalt the CPU. If the flow controller was used to  in tegra20_boot_secondary()
61 	 * power-gate the CPU this will cause the flow controller to  in tegra20_boot_secondary()
62 	 * stop driving reset. The CPU will remain in reset because the  in tegra20_boot_secondary()
65 	flowctrl_write_cpu_halt(cpu, 0);  in tegra20_boot_secondary()
67 	tegra_enable_cpu_clock(cpu);  in tegra20_boot_secondary()
68 	flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */  in tegra20_boot_secondary()
69 	tegra_cpu_out_of_reset(cpu);  in tegra20_boot_secondary()
73 static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)  in tegra30_boot_secondary()  argument
78 	cpu = cpu_logical_map(cpu);  in tegra30_boot_secondary()
79 	tegra_put_cpu_in_reset(cpu);  in tegra30_boot_secondary()
80 	flowctrl_write_cpu_halt(cpu, 0);  in tegra30_boot_secondary()
83 	 * The power up sequence of cold boot CPU and warm boot CPU  in tegra30_boot_secondary()
86 	 * For warm boot CPU that was resumed from CPU hotplug, the  in tegra30_boot_secondary()
88 	 * flow controller of the warm boot CPU. We need to wait for  in tegra30_boot_secondary()
89 	 * the confirmaiton that the CPU is powered then removing  in tegra30_boot_secondary()
91 	 * For cold boot CPU, do not wait. After the cold boot CPU be  in tegra30_boot_secondary()
96 	if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {  in tegra30_boot_secondary()
99 			if (tegra_pmc_cpu_is_powered(cpu))  in tegra30_boot_secondary()
106 	 * The power status of the cold boot CPU is power gated as  in tegra30_boot_secondary()
107 	 * default. To power up the cold boot CPU, the power should  in tegra30_boot_secondary()
111 	ret = tegra_pmc_cpu_power_on(cpu);  in tegra30_boot_secondary()
116 	/* CPU partition is powered. Enable the CPU clock. */  in tegra30_boot_secondary()
117 	tegra_enable_cpu_clock(cpu);  in tegra30_boot_secondary()
121 	ret = tegra_pmc_cpu_remove_clamping(cpu);  in tegra30_boot_secondary()
127 	flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */  in tegra30_boot_secondary()
128 	tegra_cpu_out_of_reset(cpu);  in tegra30_boot_secondary()
132 static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle)  in tegra114_boot_secondary()  argument
136 	cpu = cpu_logical_map(cpu);  in tegra114_boot_secondary()
138 	if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {  in tegra114_boot_secondary()
142 		 * control for each CPU.  in tegra114_boot_secondary()
145 		flowctrl_write_cpu_csr(cpu, 1);  in tegra114_boot_secondary()
146 		flowctrl_write_cpu_halt(cpu,  in tegra114_boot_secondary()
151 		 * The CPU is powered up by toggling PMC directly. It will  in tegra114_boot_secondary()
153 		 * the CPU's power state is maintained by flow controller.  in tegra114_boot_secondary()
155 		ret = tegra_pmc_cpu_power_on(cpu);  in tegra114_boot_secondary()
161 static int tegra_boot_secondary(unsigned int cpu,  in tegra_boot_secondary()  argument
165 		return tegra20_boot_secondary(cpu, idle);  in tegra_boot_secondary()
167 		return tegra30_boot_secondary(cpu, idle);  in tegra_boot_secondary()
169 		return tegra114_boot_secondary(cpu, idle);  in tegra_boot_secondary()
171 		return tegra114_boot_secondary(cpu, idle);  in tegra_boot_secondary()
178 	/* Always mark the boot CPU (CPU0) as initialized. */  in tegra_smp_prepare_cpus()