Lines Matching +full:0 +full:xf0ffffff
26 #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
27 #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
28 #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
29 #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
30 #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */
31 #define SLCR_L2C_RAM 0xA1C /* L2C_RAM in AR#54190 */
33 #define SLCR_UNLOCK_MAGIC 0xDF0D
34 #define SLCR_A9_CPU_CLKSTOP 0x10
35 #define SLCR_A9_CPU_RST 0x1
37 #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
48 * Return: a negative value on error, 0 on success
61 * Return: a negative value on error, 0 on success
71 * Return: a negative value on error, 0 on success
77 return 0; in zynq_slcr_unlock()
103 * Return: 0 always
112 * Clear 0x0F000000 bits of reboot status register to workaround in zynq_slcr_system_restart()
117 zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); in zynq_slcr_system_restart()
119 return 0; in zynq_slcr_system_restart()
162 * 0 means cpu is running, 1 cpu is going to die.
182 * 0 means cpu is running, 1 cpu is going to die.
200 * Return: 0 on success, negative errno otherwise.
214 zynq_slcr_base = of_iomap(np, 0); in zynq_early_slcr_init()
232 regmap_update_bits(zynq_slcr_regmap, SLCR_L2C_RAM, 0x70707, 0x20202); in zynq_early_slcr_init()
240 return 0; in zynq_early_slcr_init()