Lines Matching +full:0 +full:x00000031
23 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
47 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
48 bic r0, r0, #0x00001000 @ i-cache
49 bic r0, r0, #0x00000004 @ d-cache
50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
60 mov ip, #0
61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
64 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
65 bic ip, ip, #0x00000005 @ .............c.p
66 bic ip, ip, #0x00001000 @ i-cache
67 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
86 mov r0, #0
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
104 mov ip, #0
107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
113 bcs 2b @ entries n to 0
115 bcs 1b @ segments 3 to 0
118 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
119 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
134 mov ip, #0
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
192 mcr p15, 0, r0, c7, c10, 4 @ drain WB
193 mov r0, #0
208 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
212 mov r0, #0
213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
214 mcr p15, 0, r0, c7, c10, 4 @ drain WB
232 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
234 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
237 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
241 mcr p15, 0, r0, c7, c10, 4 @ drain WB
257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
262 mcr p15, 0, r0, c7, c10, 4 @ drain WB
279 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
331 mov r0, #0
332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
333 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
334 mcr p15, 0, r0, c7, c10, 4 @ drain WB
336 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
337 mcr p15, 0, r0, c6, c4, 0
338 mcr p15, 0, r0, c6, c5, 0
339 mcr p15, 0, r0, c6, c6, 0
340 mcr p15, 0, r0, c6, c7, 0
342 mov r0, #0x0000003F @ base = 0, size = 4GB
343 mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
345 ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
348 mcr p15, 0, r3, c6, c1, 0
350 ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
353 mcr p15, 0, r3, c6, c2, 0
355 mov r0, #0x06
356 mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
357 mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
359 mov r0, #0x00 @ disable whole write buffer
361 mov r0, #0x02 @ region 1 write bufferred
363 mcr p15, 0, r0, c3, c0, 0
369 * region 0 (whole) rw -- : b0001
374 mov r0, #0x00000031
375 orr r0, r0, #0x00000200
376 mcr p15, 0, r0, c5, c0, 2 @ set data access permission
377 mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
379 mrc p15, 0, r0, c1, c0 @ get control register
380 orr r0, r0, #0x00001000 @ I-cache
381 orr r0, r0, #0x00000005 @ MPU/D-cache
383 orr r0, r0, #0x00004000 @ .1.. .... .... ....
405 .long 0x41009460
406 .long 0xff00fff0
407 .long 0
408 .long 0
415 .long 0
416 .long 0