Lines Matching +full:0 +full:x51000000
33 * 0 0 - - Unallocated
34 * 1 0 0 - Data processing, immediate
35 * 1 0 1 - Branch, exception generation and system instructions
36 * - 1 - 0 Loads and stores
37 * - 1 0 1 Data processing - register
38 * 0 1 1 1 Data processing - SIMD and floating point
53 AARCH64_INSN_HINT_NOP = 0x0 << 5,
54 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
55 AARCH64_INSN_HINT_WFE = 0x2 << 5,
56 AARCH64_INSN_HINT_WFI = 0x3 << 5,
57 AARCH64_INSN_HINT_SEV = 0x4 << 5,
58 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
88 AARCH64_INSN_REG_0 = 0,
126 AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
127 AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
128 AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
129 AARCH64_INSN_SPCLREG_SPSEL = 0xC210,
130 AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212,
131 AARCH64_INSN_SPCLREG_DAIF = 0xDA11,
132 AARCH64_INSN_SPCLREG_NZCV = 0xDA10,
133 AARCH64_INSN_SPCLREG_FPCR = 0xDA20,
134 AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28,
135 AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29,
136 AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200,
137 AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201,
138 AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
139 AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218,
140 AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219,
141 AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A,
142 AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B,
143 AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200,
144 AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201,
145 AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
154 AARCH64_INSN_COND_EQ = 0x0, /* == */
155 AARCH64_INSN_COND_NE = 0x1, /* != */
156 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
157 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
158 AARCH64_INSN_COND_MI = 0x4, /* < 0 */
159 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
160 AARCH64_INSN_COND_VS = 0x6, /* overflow */
161 AARCH64_INSN_COND_VC = 0x7, /* no overflow */
162 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
163 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
164 AARCH64_INSN_COND_GE = 0xa, /* signed >= */
165 AARCH64_INSN_COND_LT = 0xb, /* signed < */
166 AARCH64_INSN_COND_GT = 0xc, /* signed > */
167 AARCH64_INSN_COND_LE = 0xd, /* signed <= */
168 AARCH64_INSN_COND_AL = 0xe, /* always */
270 __AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
271 __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
272 __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
273 __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
274 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
275 __AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
276 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
277 __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
278 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
279 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
280 __AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
281 __AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
282 __AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
283 __AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
284 __AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
285 __AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
286 __AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
287 __AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
288 __AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
289 __AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
290 __AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
291 __AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
292 __AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
293 __AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
294 __AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
295 __AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
296 __AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
297 __AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
298 __AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
299 __AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
300 __AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
301 __AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
302 __AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
303 __AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
304 __AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
305 __AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
306 __AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
307 __AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
308 __AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
309 __AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
310 __AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
311 __AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
312 __AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
313 __AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
314 __AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
315 __AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
316 __AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
317 __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
318 __AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
319 __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
320 __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
321 __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
322 __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
323 __AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
324 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
325 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
326 __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
327 __AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
328 __AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
329 __AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
330 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
331 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
332 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
333 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
334 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
335 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
336 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
337 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
338 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
339 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
340 __AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
341 __AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
342 __AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
343 __AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
467 #define A32_RT2_OFFSET 0