Lines Matching full:12
32 * [15-12] : CRn
40 #define CRn_shift 12
208 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
302 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
303 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
305 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
306 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
307 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
308 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
309 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
314 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
319 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
320 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
321 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
322 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
323 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
324 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
325 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
326 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
327 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
328 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
329 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
330 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
331 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
346 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
347 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
348 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
349 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
350 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
351 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
352 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
353 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
384 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
385 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
391 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
397 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
398 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
399 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
400 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
401 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
402 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
403 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
404 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
406 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
416 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
431 #define SCTLR_ELx_I (1 << 12)
519 #define ID_AA64ISAR0_SHA2_SHIFT 12
526 #define ID_AA64ISAR1_JSCVT_SHIFT 12
538 #define ID_AA64PFR0_EL3_SHIFT 12
565 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
588 #define ID_AA64MMFR1_HPD_SHIFT 12
600 #define ID_AA64MMFR2_IESB_SHIFT 12
609 #define ID_AA64DFR0_BRPS_SHIFT 12
616 #define ID_ISAR5_SHA2_SHIFT 12
625 #define MVFR0_FPTRAP_SHIFT 12
634 #define MVFR1_SIMDINT_SHIFT 12
682 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
701 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n"