Lines Matching +full:clk +full:- +full:div
30 struct clk clkin1 = {
130 struct clk c6x_core_clk = {
135 struct clk c6x_i2c_clk = {
139 struct clk c6x_watchdog_clk = {
143 struct clk c6x_mcbsp1_clk = {
147 struct clk c6x_mcbsp2_clk = {
151 struct clk c6x_mdio_clk = {
158 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
159 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
160 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
161 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
162 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
163 CLK(NULL, "core", &c6x_core_clk),
164 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
165 CLK("watchdog", NULL, &c6x_watchdog_clk),
166 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
167 CLK("", NULL, NULL)
174 struct clk *sysclks = pll->sysclks; in c6455_setup_clocks()
176 pll->flags = PLL_HAS_PRE | PLL_HAS_MUL; in c6455_setup_clocks()
179 sysclks[2].div = 3; in c6455_setup_clocks()
181 sysclks[3].div = 6; in c6455_setup_clocks()
182 sysclks[4].div = PLLDIV4; in c6455_setup_clocks()
183 sysclks[5].div = PLLDIV5; in c6455_setup_clocks()
196 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
197 CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
198 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
199 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
200 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
201 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
202 CLK(NULL, "core", &c6x_core_clk),
203 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
204 CLK("watchdog", NULL, &c6x_watchdog_clk),
205 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
206 CLK("", NULL, NULL)
212 struct clk *sysclks = pll->sysclks; in c6457_setup_clocks()
214 pll->flags = PLL_HAS_MUL | PLL_HAS_POST; in c6457_setup_clocks()
217 sysclks[1].div = 1; in c6457_setup_clocks()
219 sysclks[2].div = 3; in c6457_setup_clocks()
221 sysclks[3].div = 6; in c6457_setup_clocks()
222 sysclks[4].div = PLLDIV4; in c6457_setup_clocks()
223 sysclks[5].div = PLLDIV5; in c6457_setup_clocks()
236 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
237 CLK(NULL, "pll1_sysclk1", &c6x_soc_pll1.sysclks[1]),
238 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
239 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
240 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
241 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
242 CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
243 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
244 CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
245 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
246 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
247 CLK(NULL, "core", &c6x_core_clk),
248 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
249 CLK("watchdog", NULL, &c6x_watchdog_clk),
250 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
251 CLK("", NULL, NULL)
262 struct clk *sysclks = pll->sysclks; in c6472_setup_clocks()
265 pll->flags = PLL_HAS_MUL; in c6472_setup_clocks()
269 sysclks[i].div = 1; in c6472_setup_clocks()
273 sysclks[7].div = 3; in c6472_setup_clocks()
275 sysclks[8].div = 6; in c6472_setup_clocks()
277 sysclks[9].div = 2; in c6472_setup_clocks()
278 sysclks[10].div = PLLDIV10; in c6472_setup_clocks()
292 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
293 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
294 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
295 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
296 CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
297 CLK(NULL, "pll1_sysclk12", &c6x_soc_pll1.sysclks[12]),
298 CLK(NULL, "pll1_sysclk13", &c6x_soc_pll1.sysclks[13]),
299 CLK(NULL, "core", &c6x_core_clk),
300 CLK("i2c_davinci.1", NULL, &c6x_i2c_clk),
301 CLK("mcbsp.1", NULL, &c6x_mcbsp1_clk),
302 CLK("mcbsp.2", NULL, &c6x_mcbsp2_clk),
303 CLK("watchdog", NULL, &c6x_watchdog_clk),
304 CLK("2c81800.mdio", NULL, &c6x_mdio_clk),
305 CLK("", NULL, NULL)
311 struct clk *sysclks = pll->sysclks; in c6474_setup_clocks()
313 pll->flags = PLL_HAS_MUL; in c6474_setup_clocks()
316 sysclks[7].div = 1; in c6474_setup_clocks()
318 sysclks[9].div = 3; in c6474_setup_clocks()
320 sysclks[10].div = 6; in c6474_setup_clocks()
322 sysclks[11].div = PLLDIV11; in c6474_setup_clocks()
325 sysclks[12].div = 2; in c6474_setup_clocks()
327 sysclks[13].div = PLLDIV13; in c6474_setup_clocks()
341 CLK(NULL, "pll1", &c6x_soc_pll1.sysclks[0]),
342 CLK(NULL, "pll1_refclk", &c6x_soc_pll1.sysclks[1]),
343 CLK(NULL, "pll1_sysclk2", &c6x_soc_pll1.sysclks[2]),
344 CLK(NULL, "pll1_sysclk3", &c6x_soc_pll1.sysclks[3]),
345 CLK(NULL, "pll1_sysclk4", &c6x_soc_pll1.sysclks[4]),
346 CLK(NULL, "pll1_sysclk5", &c6x_soc_pll1.sysclks[5]),
347 CLK(NULL, "pll1_sysclk6", &c6x_soc_pll1.sysclks[6]),
348 CLK(NULL, "pll1_sysclk7", &c6x_soc_pll1.sysclks[7]),
349 CLK(NULL, "pll1_sysclk8", &c6x_soc_pll1.sysclks[8]),
350 CLK(NULL, "pll1_sysclk9", &c6x_soc_pll1.sysclks[9]),
351 CLK(NULL, "pll1_sysclk10", &c6x_soc_pll1.sysclks[10]),
352 CLK(NULL, "pll1_sysclk11", &c6x_soc_pll1.sysclks[11]),
353 CLK(NULL, "core", &c6x_core_clk),
354 CLK("", NULL, NULL)
360 struct clk *sysclks = pll->sysclks; in c6678_setup_clocks()
362 pll->flags = PLL_HAS_MUL; in c6678_setup_clocks()
365 sysclks[1].div = 1; in c6678_setup_clocks()
367 sysclks[2].div = PLLDIV2; in c6678_setup_clocks()
370 sysclks[3].div = 2; in c6678_setup_clocks()
373 sysclks[4].div = 3; in c6678_setup_clocks()
375 sysclks[5].div = PLLDIV5; in c6678_setup_clocks()
378 sysclks[6].div = 64; in c6678_setup_clocks()
381 sysclks[7].div = 6; in c6678_setup_clocks()
383 sysclks[8].div = PLLDIV8; in c6678_setup_clocks()
386 sysclks[9].div = 12; in c6678_setup_clocks()
389 sysclks[10].div = 3; in c6678_setup_clocks()
392 sysclks[11].div = 6; in c6678_setup_clocks()
403 { .compatible = "ti,c6455-pll", .data = c6455_setup_clocks },
406 { .compatible = "ti,c6457-pll", .data = c6457_setup_clocks },
409 { .compatible = "ti,c6472-pll", .data = c6472_setup_clocks },
412 { .compatible = "ti,c6474-pll", .data = c6474_setup_clocks },
415 { .compatible = "ti,c6678-pll", .data = c6678_setup_clocks },
434 pll->base = of_iomap(node, 0); in c64x_setup_clocks()
435 if (!pll->base) in c64x_setup_clocks()
438 err = of_property_read_u32(node, "clock-frequency", &val); in c64x_setup_clocks()
440 pr_err("%pOF: no clock-frequency found! Using %dMHz\n", in c64x_setup_clocks()
446 err = of_property_read_u32(node, "ti,c64x+pll-bypass-delay", &val); in c64x_setup_clocks()
449 pll->bypass_delay = val; in c64x_setup_clocks()
451 err = of_property_read_u32(node, "ti,c64x+pll-reset-delay", &val); in c64x_setup_clocks()
454 pll->reset_delay = val; in c64x_setup_clocks()
456 err = of_property_read_u32(node, "ti,c64x+pll-lock-delay", &val); in c64x_setup_clocks()
459 pll->lock_delay = val; in c64x_setup_clocks()
461 /* id->data is a pointer to SoC-specific setup */ in c64x_setup_clocks()
463 if (id && id->data) { in c64x_setup_clocks()
464 __setup_clocks = id->data; in c64x_setup_clocks()