Lines Matching +full:bus +full:- +full:range
11 * Common pmac/prep/chrp pci routines. -- Cort
39 #include <asm/pci-bridge.h>
64 phb->global_number = global_phb_number++; in pcibios_alloc_controller()
65 list_add_tail(&phb->list_node, &hose_list); in pcibios_alloc_controller()
67 phb->dn = dev; in pcibios_alloc_controller()
68 phb->is_dynamic = mem_init_done; in pcibios_alloc_controller()
75 list_del(&phb->list_node); in pcibios_free_controller()
78 if (phb->is_dynamic) in pcibios_free_controller()
84 return resource_size(&hose->io_resource); in pcibios_io_size()
96 if (address >= hose->io_base_virt && in pcibios_vaddr_is_ioport()
97 address < (hose->io_base_virt + size)) { in pcibios_vaddr_is_ioport()
115 if (address >= hose->io_base_phys && in pci_address_to_pio()
116 address < (hose->io_base_phys + size)) { in pci_address_to_pio()
118 (unsigned long)hose->io_base_virt - _IO_BASE; in pci_address_to_pio()
119 ret = base + (address - hose->io_base_phys); in pci_address_to_pio()
130 * PCI bus numbers have not yet been assigned, and you need to
141 if (hose->dn == node) in pci_find_hose_for_OF_device()
143 node = node->parent; in pci_find_hose_for_OF_device()
150 /* No special bus mastering setup handling */ in pcibios_set_master()
154 * Platform support for /proc/bus/pci/X/Y mmap()s.
159 struct pci_controller *hose = pci_bus_to_host(pdev->bus); in pci_iobar_pfn()
163 return -EINVAL; /* should never happen */ in pci_iobar_pfn()
166 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; in pci_iobar_pfn()
168 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; in pci_iobar_pfn()
193 struct resource *rp = &pdev->resource[i]; in pci_phys_mem_access_prot()
194 int flags = rp->flags; in pci_phys_mem_access_prot()
199 /* In the range of this resource? */ in pci_phys_mem_access_prot()
200 if (offset < (rp->start & PAGE_MASK) || in pci_phys_mem_access_prot()
201 offset > rp->end) in pci_phys_mem_access_prot()
210 if (found->flags & IORESOURCE_PREFETCH) in pci_phys_mem_access_prot()
215 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", in pci_phys_mem_access_prot()
221 /* This provides legacy IO read access on a bus */
222 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) in pci_legacy_read() argument
225 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_read()
226 struct resource *rp = &hose->io_resource; in pci_legacy_read()
229 /* Check if port can be supported by that bus. We only check in pci_legacy_read()
230 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_read()
234 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_read()
237 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_read()
238 return -ENXIO; in pci_legacy_read()
239 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_read()
240 return -ENXIO; in pci_legacy_read()
241 addr = hose->io_base_virt + port; in pci_legacy_read()
249 return -EINVAL; in pci_legacy_read()
254 return -EINVAL; in pci_legacy_read()
258 return -EINVAL; in pci_legacy_read()
261 /* This provides legacy IO write access on a bus */
262 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) in pci_legacy_write() argument
265 struct pci_controller *hose = pci_bus_to_host(bus); in pci_legacy_write()
266 struct resource *rp = &hose->io_resource; in pci_legacy_write()
269 /* Check if port can be supported by that bus. We only check in pci_legacy_write()
270 * the ranges of the PHB though, not the bus itself as the rules in pci_legacy_write()
274 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pci_legacy_write()
277 if (!(rp->flags & IORESOURCE_IO)) in pci_legacy_write()
278 return -ENXIO; in pci_legacy_write()
279 if (offset < rp->start || (offset + size) > rp->end) in pci_legacy_write()
280 return -ENXIO; in pci_legacy_write()
281 addr = hose->io_base_virt + port; in pci_legacy_write()
294 return -EINVAL; in pci_legacy_write()
299 return -EINVAL; in pci_legacy_write()
303 return -EINVAL; in pci_legacy_write()
306 /* This provides legacy IO or memory mmap access on a bus */
307 int pci_mmap_legacy_page_range(struct pci_bus *bus, in pci_mmap_legacy_page_range() argument
311 struct pci_controller *hose = pci_bus_to_host(bus); in pci_mmap_legacy_page_range()
313 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; in pci_mmap_legacy_page_range()
314 resource_size_t size = vma->vm_end - vma->vm_start; in pci_mmap_legacy_page_range()
318 pci_domain_nr(bus), bus->number, in pci_mmap_legacy_page_range()
321 (unsigned long long)(offset + size - 1)); in pci_mmap_legacy_page_range()
331 if ((offset + size) > hose->isa_mem_size) { in pci_mmap_legacy_page_range()
333 pr_debug("Process %s (pid:%d) mapped non-existing PCI", in pci_mmap_legacy_page_range()
334 current->comm, current->pid); in pci_mmap_legacy_page_range()
336 pci_domain_nr(bus), bus->number); in pci_mmap_legacy_page_range()
338 if (vma->vm_flags & VM_SHARED) in pci_mmap_legacy_page_range()
342 offset += hose->isa_mem_phys; in pci_mmap_legacy_page_range()
344 unsigned long io_offset = (unsigned long)hose->io_base_virt - in pci_mmap_legacy_page_range()
347 rp = &hose->io_resource; in pci_mmap_legacy_page_range()
348 if (!(rp->flags & IORESOURCE_IO)) in pci_mmap_legacy_page_range()
349 return -ENXIO; in pci_mmap_legacy_page_range()
350 if (roffset < rp->start || (roffset + size) > rp->end) in pci_mmap_legacy_page_range()
351 return -ENXIO; in pci_mmap_legacy_page_range()
352 offset += hose->io_base_phys; in pci_mmap_legacy_page_range()
354 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); in pci_mmap_legacy_page_range()
356 vma->vm_pgoff = offset >> PAGE_SHIFT; in pci_mmap_legacy_page_range()
357 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); in pci_mmap_legacy_page_range()
358 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, in pci_mmap_legacy_page_range()
359 vma->vm_end - vma->vm_start, in pci_mmap_legacy_page_range()
360 vma->vm_page_prot); in pci_mmap_legacy_page_range()
369 if (rsrc->flags & IORESOURCE_IO) { in pci_resource_to_user()
370 pcibios_resource_to_bus(dev->bus, ®ion, in pci_resource_to_user()
381 * That means we may have 64-bit values where some apps only expect in pci_resource_to_user()
382 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO). in pci_resource_to_user()
384 *start = rsrc->start; in pci_resource_to_user()
385 *end = rsrc->end; in pci_resource_to_user()
389 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
392 * @primary: set if primary bus (32 bits only, soon to be deprecated)
401 * - We can only cope with one IO space range and up to 3 Memory space
405 * - We can only cope with all memory ranges having the same offset
414 * - Some busses have IO space not starting at 0, which causes trouble with
418 * - Some 32 bits platforms such as 4xx can have physical space larger than
424 int memno = 0, isa_hole = -1; in pci_process_bridge_OF_ranges()
427 struct of_pci_range range; in pci_process_bridge_OF_ranges() local
438 for_each_of_pci_range(&parser, &range) { in pci_process_bridge_OF_ranges()
441 range.pci_space, range.pci_addr); in pci_process_bridge_OF_ranges()
443 range.cpu_addr, range.size); in pci_process_bridge_OF_ranges()
445 /* If we failed translation or got a zero-sized region in pci_process_bridge_OF_ranges()
450 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) in pci_process_bridge_OF_ranges()
455 switch (range.flags & IORESOURCE_TYPE_BITS) { in pci_process_bridge_OF_ranges()
457 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", in pci_process_bridge_OF_ranges()
458 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
459 range.pci_addr); in pci_process_bridge_OF_ranges()
461 /* We support only one IO range */ in pci_process_bridge_OF_ranges()
462 if (hose->pci_io_size) { in pci_process_bridge_OF_ranges()
463 pr_info(" \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
467 if (range.size > 0x01000000) in pci_process_bridge_OF_ranges()
468 range.size = 0x01000000; in pci_process_bridge_OF_ranges()
471 hose->io_base_virt = ioremap(range.cpu_addr, in pci_process_bridge_OF_ranges()
472 range.size); in pci_process_bridge_OF_ranges()
477 (unsigned long)hose->io_base_virt; in pci_process_bridge_OF_ranges()
481 hose->pci_io_size = range.pci_addr + range.size; in pci_process_bridge_OF_ranges()
482 hose->io_base_phys = range.cpu_addr - range.pci_addr; in pci_process_bridge_OF_ranges()
485 res = &hose->io_resource; in pci_process_bridge_OF_ranges()
486 range.cpu_addr = range.pci_addr; in pci_process_bridge_OF_ranges()
490 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", in pci_process_bridge_OF_ranges()
491 range.cpu_addr, range.cpu_addr + range.size - 1, in pci_process_bridge_OF_ranges()
492 range.pci_addr, in pci_process_bridge_OF_ranges()
493 (range.pci_space & 0x40000000) ? in pci_process_bridge_OF_ranges()
498 pr_info(" \\--> Skipped (too many) !\n"); in pci_process_bridge_OF_ranges()
502 if (range.pci_addr == 0) { in pci_process_bridge_OF_ranges()
503 isa_mb = range.cpu_addr; in pci_process_bridge_OF_ranges()
506 isa_mem_base = range.cpu_addr; in pci_process_bridge_OF_ranges()
507 hose->isa_mem_phys = range.cpu_addr; in pci_process_bridge_OF_ranges()
508 hose->isa_mem_size = range.size; in pci_process_bridge_OF_ranges()
511 /* We get the PCI/Mem offset from the first range or in pci_process_bridge_OF_ranges()
516 (isa_hole >= 0 && range.pci_addr != 0 && in pci_process_bridge_OF_ranges()
517 hose->pci_mem_offset == isa_mb)) in pci_process_bridge_OF_ranges()
518 hose->pci_mem_offset = range.cpu_addr - in pci_process_bridge_OF_ranges()
519 range.pci_addr; in pci_process_bridge_OF_ranges()
520 else if (range.pci_addr != 0 && in pci_process_bridge_OF_ranges()
521 hose->pci_mem_offset != range.cpu_addr - in pci_process_bridge_OF_ranges()
522 range.pci_addr) { in pci_process_bridge_OF_ranges()
523 pr_info(" \\--> Skipped (offset mismatch) !\n"); in pci_process_bridge_OF_ranges()
528 res = &hose->mem_resources[memno++]; in pci_process_bridge_OF_ranges()
532 res->name = dev->full_name; in pci_process_bridge_OF_ranges()
533 res->flags = range.flags; in pci_process_bridge_OF_ranges()
534 res->start = range.cpu_addr; in pci_process_bridge_OF_ranges()
535 res->end = range.cpu_addr + range.size - 1; in pci_process_bridge_OF_ranges()
536 res->parent = res->child = res->sibling = NULL; in pci_process_bridge_OF_ranges()
540 /* If there's an ISA hole and the pci_mem_offset is -not- matching in pci_process_bridge_OF_ranges()
544 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { in pci_process_bridge_OF_ranges()
548 memmove(&hose->mem_resources[isa_hole], in pci_process_bridge_OF_ranges()
549 &hose->mem_resources[next], in pci_process_bridge_OF_ranges()
550 sizeof(struct resource) * (memno - next)); in pci_process_bridge_OF_ranges()
551 hose->mem_resources[--memno].flags = 0; in pci_process_bridge_OF_ranges()
556 int pci_proc_domain(struct pci_bus *bus) in pci_proc_domain() argument
558 return pci_domain_nr(bus); in pci_proc_domain()
566 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pcibios_fixup_resources()
575 struct resource *res = dev->resource + i; in pcibios_fixup_resources()
576 if (!res->flags) in pcibios_fixup_resources()
578 if (res->start == 0) { in pcibios_fixup_resources()
579 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", in pcibios_fixup_resources()
581 (unsigned long long)res->start, in pcibios_fixup_resources()
582 (unsigned long long)res->end, in pcibios_fixup_resources()
583 (unsigned int)res->flags); in pcibios_fixup_resources()
585 res->end -= res->start; in pcibios_fixup_resources()
586 res->start = 0; in pcibios_fixup_resources()
587 res->flags |= IORESOURCE_UNSET; in pcibios_fixup_resources()
591 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", in pcibios_fixup_resources()
593 (unsigned long long)res->start, in pcibios_fixup_resources()
594 (unsigned long long)res->end, in pcibios_fixup_resources()
595 (unsigned int)res->flags); in pcibios_fixup_resources()
602 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); in pcibios_add_device()
618 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { in reparent_resources()
619 if (p->end < res->start) in reparent_resources()
621 if (res->end < p->start) in reparent_resources()
623 if (p->start < res->start || p->end > res->end) in reparent_resources()
624 return -1; /* not completely contained */ in reparent_resources()
629 return -1; /* didn't find any conflicting entries? */ in reparent_resources()
630 res->parent = parent; in reparent_resources()
631 res->child = *firstpp; in reparent_resources()
632 res->sibling = *pp; in reparent_resources()
635 for (p = res->child; p != NULL; p = p->sibling) { in reparent_resources()
636 p->parent = res; in reparent_resources()
638 p->name, in reparent_resources()
639 (unsigned long long)p->start, in reparent_resources()
640 (unsigned long long)p->end, res->name); in reparent_resources()
648 * On the other hand, we cannot just re-allocate all devices, as it would
654 * - I/O or memory regions not configured
655 * - regions configured, but not enabled in the command register
656 * - bogus I/O addresses above 64K used
657 * - expansion ROMs left enabled (this may sound harmless, but given
663 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
678 static void pcibios_allocate_bus_resources(struct pci_bus *bus) in pcibios_allocate_bus_resources() argument
684 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", in pcibios_allocate_bus_resources()
685 pci_domain_nr(bus), bus->number); in pcibios_allocate_bus_resources()
687 pci_bus_for_each_resource(bus, res, i) { in pcibios_allocate_bus_resources()
688 if (!res || !res->flags in pcibios_allocate_bus_resources()
689 || res->start > res->end || res->parent) in pcibios_allocate_bus_resources()
691 if (bus->parent == NULL) in pcibios_allocate_bus_resources()
692 pr = (res->flags & IORESOURCE_IO) ? in pcibios_allocate_bus_resources()
695 /* Don't bother with non-root busses when in pcibios_allocate_bus_resources()
696 * re-assigning all resources. We clear the in pcibios_allocate_bus_resources()
698 * and as such ensure proper re-allocation in pcibios_allocate_bus_resources()
701 pr = pci_find_parent_resource(bus->self, res); in pcibios_allocate_bus_resources()
705 * bridge is transparent -- paulus in pcibios_allocate_bus_resources()
711 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", in pcibios_allocate_bus_resources()
712 bus->self ? pci_name(bus->self) : "PHB", in pcibios_allocate_bus_resources()
713 bus->number, i, in pcibios_allocate_bus_resources()
714 (unsigned long long)res->start, in pcibios_allocate_bus_resources()
715 (unsigned long long)res->end); in pcibios_allocate_bus_resources()
717 (unsigned int)res->flags, in pcibios_allocate_bus_resources()
718 pr, (pr && pr->name) ? pr->name : "nil"); in pcibios_allocate_bus_resources()
720 if (pr && !(pr->flags & IORESOURCE_UNSET)) { in pcibios_allocate_bus_resources()
721 struct pci_dev *dev = bus->self; in pcibios_allocate_bus_resources()
740 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); in pcibios_allocate_bus_resources()
741 res->start = res->end = 0; in pcibios_allocate_bus_resources()
742 res->flags = 0; in pcibios_allocate_bus_resources()
745 list_for_each_entry(b, &bus->children, node) in pcibios_allocate_bus_resources()
751 struct resource *pr, *r = &dev->resource[idx]; in alloc_resource()
755 (unsigned long long)r->start, in alloc_resource()
756 (unsigned long long)r->end, in alloc_resource()
757 (unsigned int)r->flags); in alloc_resource()
760 if (!pr || (pr->flags & IORESOURCE_UNSET) || in alloc_resource()
765 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", in alloc_resource()
767 (unsigned long long)pr->start, in alloc_resource()
768 (unsigned long long)pr->end, in alloc_resource()
769 (unsigned int)pr->flags); in alloc_resource()
771 r->flags |= IORESOURCE_UNSET; in alloc_resource()
772 r->end -= r->start; in alloc_resource()
773 r->start = 0; in alloc_resource()
787 r = &dev->resource[idx]; in pcibios_allocate_resources()
788 if (r->parent) /* Already allocated */ in pcibios_allocate_resources()
790 if (!r->flags || (r->flags & IORESOURCE_UNSET)) in pcibios_allocate_resources()
797 if (r->flags & IORESOURCE_IO) in pcibios_allocate_resources()
806 r = &dev->resource[PCI_ROM_RESOURCE]; in pcibios_allocate_resources()
807 if (r->flags) { in pcibios_allocate_resources()
812 pci_read_config_dword(dev, dev->rom_base_reg, ®); in pcibios_allocate_resources()
816 r->flags &= ~IORESOURCE_ROM_ENABLE; in pcibios_allocate_resources()
817 pci_write_config_dword(dev, dev->rom_base_reg, in pcibios_allocate_resources()
824 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) in pcibios_reserve_legacy_regions() argument
826 struct pci_controller *hose = pci_bus_to_host(bus); in pcibios_reserve_legacy_regions()
832 pci_domain_nr(bus)); in pcibios_reserve_legacy_regions()
835 if (!(hose->io_resource.flags & IORESOURCE_IO)) in pcibios_reserve_legacy_regions()
837 offset = (unsigned long)hose->io_base_virt - _IO_BASE; in pcibios_reserve_legacy_regions()
840 res->name = "Legacy IO"; in pcibios_reserve_legacy_regions()
841 res->flags = IORESOURCE_IO; in pcibios_reserve_legacy_regions()
842 res->start = offset; in pcibios_reserve_legacy_regions()
843 res->end = (offset + 0xfff) & 0xfffffffful; in pcibios_reserve_legacy_regions()
845 if (request_resource(&hose->io_resource, res)) { in pcibios_reserve_legacy_regions()
847 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
853 offset = hose->pci_mem_offset; in pcibios_reserve_legacy_regions()
856 pres = &hose->mem_resources[i]; in pcibios_reserve_legacy_regions()
857 if (!(pres->flags & IORESOURCE_MEM)) in pcibios_reserve_legacy_regions()
860 if ((pres->start - offset) <= 0xa0000 && in pcibios_reserve_legacy_regions()
861 (pres->end - offset) >= 0xbffff) in pcibios_reserve_legacy_regions()
868 res->name = "Legacy VGA memory"; in pcibios_reserve_legacy_regions()
869 res->flags = IORESOURCE_MEM; in pcibios_reserve_legacy_regions()
870 res->start = 0xa0000 + offset; in pcibios_reserve_legacy_regions()
871 res->end = 0xbffff + offset; in pcibios_reserve_legacy_regions()
875 pci_domain_nr(bus), bus->number, res); in pcibios_reserve_legacy_regions()
884 /* Allocate and assign resources. If we re-assign everything, then in pcibios_resource_survey()
895 * bus available resources to avoid allocating things on top of them in pcibios_resource_survey()
913 res = &hose->io_resource; in pcibios_setup_phb_resources()
916 io_offset = (unsigned long)hose->io_base_virt - isa_io_base; in pcibios_setup_phb_resources()
917 res->start = (res->start + io_offset) & 0xffffffffu; in pcibios_setup_phb_resources()
918 res->end = (res->end + io_offset) & 0xffffffffu; in pcibios_setup_phb_resources()
920 if (!res->flags) { in pcibios_setup_phb_resources()
923 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
924 /* Workaround for lack of IO resource only on 32-bit */ in pcibios_setup_phb_resources()
925 res->start = (unsigned long)hose->io_base_virt - isa_io_base; in pcibios_setup_phb_resources()
926 res->end = res->start + IO_SPACE_LIMIT; in pcibios_setup_phb_resources()
927 res->flags = IORESOURCE_IO; in pcibios_setup_phb_resources()
930 (__force resource_size_t)(hose->io_base_virt - _IO_BASE)); in pcibios_setup_phb_resources()
932 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", in pcibios_setup_phb_resources()
933 (unsigned long long)res->start, in pcibios_setup_phb_resources()
934 (unsigned long long)res->end, in pcibios_setup_phb_resources()
935 (unsigned long)res->flags); in pcibios_setup_phb_resources()
939 res = &hose->mem_resources[i]; in pcibios_setup_phb_resources()
940 if (!res->flags) { in pcibios_setup_phb_resources()
945 hose->dn, hose->global_number); in pcibios_setup_phb_resources()
947 /* Workaround for lack of MEM resource only on 32-bit */ in pcibios_setup_phb_resources()
948 res->start = hose->pci_mem_offset; in pcibios_setup_phb_resources()
949 res->end = (resource_size_t)-1LL; in pcibios_setup_phb_resources()
950 res->flags = IORESOURCE_MEM; in pcibios_setup_phb_resources()
953 pci_add_resource_offset(resources, res, hose->pci_mem_offset); in pcibios_setup_phb_resources()
955 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", in pcibios_setup_phb_resources()
956 i, (unsigned long long)res->start, in pcibios_setup_phb_resources()
957 (unsigned long long)res->end, in pcibios_setup_phb_resources()
958 (unsigned long)res->flags); in pcibios_setup_phb_resources()
962 (unsigned long long)hose->pci_mem_offset); in pcibios_setup_phb_resources()
964 (unsigned long)hose->io_base_virt - _IO_BASE); in pcibios_setup_phb_resources()
970 struct pci_bus *bus; in pcibios_scan_phb() local
971 struct device_node *node = hose->dn; in pcibios_scan_phb()
977 bus = pci_scan_root_bus(hose->parent, hose->first_busno, in pcibios_scan_phb()
978 hose->ops, hose, &resources); in pcibios_scan_phb()
979 if (bus == NULL) { in pcibios_scan_phb()
980 pr_err("Failed to create bus for PCI domain %04x\n", in pcibios_scan_phb()
981 hose->global_number); in pcibios_scan_phb()
985 bus->busn_res.start = hose->first_busno; in pcibios_scan_phb()
986 hose->bus = bus; in pcibios_scan_phb()
988 hose->last_busno = bus->busn_res.end; in pcibios_scan_phb()
1000 hose->last_busno = 0xff; in pcibios_init()
1002 if (next_busno <= hose->last_busno) in pcibios_init()
1003 next_busno = hose->last_busno + 1; in pcibios_init()
1010 if (hose->bus) in pcibios_init()
1011 pci_bus_add_devices(hose->bus); in pcibios_init()
1019 static struct pci_controller *pci_bus_to_hose(int bus) in pci_bus_to_hose() argument
1024 if (bus >= hose->first_busno && bus <= hose->last_busno) in pci_bus_to_hose()
1030 * memory. Do this on a per-card basis so that we choose the right
1035 long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) in sys_pciconfig_iobase() argument
1038 long result = -EOPNOTSUPP; in sys_pciconfig_iobase()
1040 hose = pci_bus_to_hose(bus); in sys_pciconfig_iobase()
1042 return -ENODEV; in sys_pciconfig_iobase()
1046 return (long)hose->first_busno; in sys_pciconfig_iobase()
1048 return (long)hose->pci_mem_offset; in sys_pciconfig_iobase()
1050 return (long)hose->io_base_phys; in sys_pciconfig_iobase()
1072 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_read_config() argument
1079 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, in null_write_config() argument
1097 static struct pci_bus bus; in fake_pci_bus() local
1100 pr_err("Can't find hose for PCI bus %d!\n", busnr); in fake_pci_bus()
1102 bus.number = busnr; in fake_pci_bus()
1103 bus.sysdata = hose; in fake_pci_bus()
1104 bus.ops = hose ? hose->ops : &null_pci_ops; in fake_pci_bus()
1105 return &bus; in fake_pci_bus()
1109 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1112 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1123 int early_find_capability(struct pci_controller *hose, int bus, int devfn, in EARLY_PCI_OP()
1126 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); in EARLY_PCI_OP()