Lines Matching +full:2 +full:c
14 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
20 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
24 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
143 preset_lpj /= 2 * HZ; in alchemy_set_lpj()
238 struct clk *c; in alchemy_clk_setup_aux() local
255 c = clk_register(NULL, &a->hw); in alchemy_clk_setup_aux()
256 if (!IS_ERR(c)) in alchemy_clk_setup_aux()
257 clk_register_clkdev(c, name, NULL); in alchemy_clk_setup_aux()
261 return c; in alchemy_clk_setup_aux()
268 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2; in alchemy_clk_setup_sysbus()
269 struct clk *c; in alchemy_clk_setup_sysbus() local
271 c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK, in alchemy_clk_setup_sysbus()
273 if (!IS_ERR(c)) in alchemy_clk_setup_sysbus()
274 clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL); in alchemy_clk_setup_sysbus()
275 return c; in alchemy_clk_setup_sysbus()
283 struct clk *c; in alchemy_clk_setup_periph() local
285 c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK, in alchemy_clk_setup_periph()
286 pn, 0, 1, 2); in alchemy_clk_setup_periph()
287 if (!IS_ERR(c)) in alchemy_clk_setup_periph()
288 clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL); in alchemy_clk_setup_periph()
289 return c; in alchemy_clk_setup_periph()
298 struct clk *c; in alchemy_clk_setup_mem() local
305 div = (v & (1 << 15)) ? 1 : 2; in alchemy_clk_setup_mem()
309 div = (v & (1 << 31)) ? 1 : 2; in alchemy_clk_setup_mem()
315 div = 2; in alchemy_clk_setup_mem()
319 c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn, in alchemy_clk_setup_mem()
321 if (!IS_ERR(c)) in alchemy_clk_setup_mem()
322 clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL); in alchemy_clk_setup_mem()
323 return c; in alchemy_clk_setup_mem()
337 struct clk *c; in alchemy_clk_setup_lrclk() local
348 c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK, in alchemy_clk_setup_lrclk()
350 if (!IS_ERR(c)) in alchemy_clk_setup_lrclk()
351 clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL); in alchemy_clk_setup_lrclk()
352 return c; in alchemy_clk_setup_lrclk()
378 if (scale == 2) { /* only div-by-multiple-of-2 possible */ in alchemy_calc_div()
486 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_en() local
489 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv1_en()
490 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_en()
491 v |= (1 << 1) << c->shift; in alchemy_clk_fgv1_en()
492 alchemy_wrsys(v, c->reg); in alchemy_clk_fgv1_en()
493 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv1_en()
500 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_isen() local
501 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); in alchemy_clk_fgv1_isen()
508 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_dis() local
511 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv1_dis()
512 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_dis()
513 v &= ~((1 << 1) << c->shift); in alchemy_clk_fgv1_dis()
514 alchemy_wrsys(v, c->reg); in alchemy_clk_fgv1_dis()
515 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv1_dis()
520 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_setp() local
523 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv1_setp()
524 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setp()
526 v |= (1 << c->shift); in alchemy_clk_fgv1_setp()
528 v &= ~(1 << c->shift); in alchemy_clk_fgv1_setp()
529 alchemy_wrsys(v, c->reg); in alchemy_clk_fgv1_setp()
530 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv1_setp()
537 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_getp() local
539 return (alchemy_rdsys(c->reg) >> c->shift) & 1; in alchemy_clk_fgv1_getp()
545 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_setr() local
547 int sh = c->shift + 2; in alchemy_clk_fgv1_setr()
549 if (!rate || !parent_rate || rate > (parent_rate / 2)) in alchemy_clk_fgv1_setr()
551 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div); in alchemy_clk_fgv1_setr()
552 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv1_setr()
553 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setr()
556 alchemy_wrsys(v, c->reg); in alchemy_clk_fgv1_setr()
557 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv1_setr()
565 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv1_recalc() local
566 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); in alchemy_clk_fgv1_recalc()
568 v = ((v & 0xff) + 1) * 2; in alchemy_clk_fgv1_recalc()
575 return alchemy_clk_fgcs_detr(hw, req, 2, 512); in alchemy_clk_fgv1_detr()
590 static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c) in __alchemy_clk_fgv2_en() argument
592 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_fgv2_en()
594 v &= ~(3 << c->shift); in __alchemy_clk_fgv2_en()
595 v |= (c->parent & 3) << c->shift; in __alchemy_clk_fgv2_en()
596 alchemy_wrsys(v, c->reg); in __alchemy_clk_fgv2_en()
597 c->isen = 1; in __alchemy_clk_fgv2_en()
602 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_en() local
606 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv2_en()
607 __alchemy_clk_fgv2_en(c); in alchemy_clk_fgv2_en()
608 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv2_en()
615 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_isen() local
617 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; in alchemy_clk_fgv2_isen()
622 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_dis() local
625 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv2_dis()
626 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_dis()
627 v &= ~(3 << c->shift); /* set input mux to "disabled" state */ in alchemy_clk_fgv2_dis()
628 alchemy_wrsys(v, c->reg); in alchemy_clk_fgv2_dis()
629 c->isen = 0; in alchemy_clk_fgv2_dis()
630 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv2_dis()
635 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_setp() local
638 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv2_setp()
639 c->parent = index + 1; /* value to write to register */ in alchemy_clk_fgv2_setp()
640 if (c->isen) in alchemy_clk_fgv2_setp()
641 __alchemy_clk_fgv2_en(c); in alchemy_clk_fgv2_setp()
642 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv2_setp()
649 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_getp() local
652 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv2_getp()
653 v = c->parent - 1; in alchemy_clk_fgv2_getp()
654 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv2_getp()
658 /* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
660 * of 2); with the bit set, dividers are multiples of 1, halving their
666 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_setr() local
667 int sh = c->shift + 2; in alchemy_clk_fgv2_setr()
673 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ in alchemy_clk_fgv2_setr()
674 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2, in alchemy_clk_fgv2_setr()
677 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_fgv2_setr()
678 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_setr()
681 alchemy_wrsys(v, c->reg); in alchemy_clk_fgv2_setr()
682 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_fgv2_setr()
690 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_recalc() local
691 int sh = c->shift + 2; in alchemy_clk_fgv2_recalc()
694 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_recalc()
697 t /= 2; in alchemy_clk_fgv2_recalc()
705 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_fgv2_detr() local
708 if (alchemy_rdsys(c->reg) & (1 << 30)) { in alchemy_clk_fgv2_detr()
712 scale = 2; in alchemy_clk_fgv2_detr()
745 struct clk *c; in alchemy_clk_init_fgens() local
755 id.num_parents = 2; in alchemy_clk_init_fgens()
777 if (i > 2) { in alchemy_clk_init_fgens()
799 c = clk_register(NULL, &a->hw); in alchemy_clk_init_fgens()
800 if (IS_ERR(c)) in alchemy_clk_init_fgens()
803 clk_register_clkdev(c, id.name, NULL); in alchemy_clk_init_fgens()
814 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_isen() local
815 unsigned long v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_isen()
817 return (((v >> c->shift) >> 2) & 7) != 0; in alchemy_clk_csrc_isen()
820 static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c) in __alchemy_clk_csrc_en() argument
822 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_csrc_en()
824 v &= ~((7 << 2) << c->shift); in __alchemy_clk_csrc_en()
825 v |= ((c->parent & 7) << 2) << c->shift; in __alchemy_clk_csrc_en()
826 alchemy_wrsys(v, c->reg); in __alchemy_clk_csrc_en()
827 c->isen = 1; in __alchemy_clk_csrc_en()
832 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_en() local
836 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_csrc_en()
837 __alchemy_clk_csrc_en(c); in alchemy_clk_csrc_en()
838 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_csrc_en()
845 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_dis() local
848 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_csrc_dis()
849 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_dis()
850 v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */ in alchemy_clk_csrc_dis()
851 alchemy_wrsys(v, c->reg); in alchemy_clk_csrc_dis()
852 c->isen = 0; in alchemy_clk_csrc_dis()
853 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_csrc_dis()
858 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_setp() local
861 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_csrc_setp()
862 c->parent = index + 1; /* value to write to register */ in alchemy_clk_csrc_setp()
863 if (c->isen) in alchemy_clk_csrc_setp()
864 __alchemy_clk_csrc_en(c); in alchemy_clk_csrc_setp()
865 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_csrc_setp()
872 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_getp() local
874 return c->parent - 1; in alchemy_clk_csrc_getp()
880 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_recalc() local
881 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; in alchemy_clk_csrc_recalc()
883 return parent_rate / c->dt[v]; in alchemy_clk_csrc_recalc()
889 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_setr() local
896 d = (parent_rate + (rate / 2)) / rate; in alchemy_clk_csrc_setr()
899 if ((d == 3) && (c->dt[2] != 3)) in alchemy_clk_csrc_setr()
903 if (c->dt[i] == d) in alchemy_clk_csrc_setr()
909 spin_lock_irqsave(c->reglock, flags); in alchemy_clk_csrc_setr()
910 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_setr()
911 v &= ~(3 << c->shift); in alchemy_clk_csrc_setr()
912 v |= (i & 3) << c->shift; in alchemy_clk_csrc_setr()
913 alchemy_wrsys(v, c->reg); in alchemy_clk_csrc_setr()
914 spin_unlock_irqrestore(c->reglock, flags); in alchemy_clk_csrc_setr()
922 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw); in alchemy_clk_csrc_detr() local
923 int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */ in alchemy_clk_csrc_detr()
946 static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
947 static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
956 struct clk *c; in alchemy_clk_setup_imux() local
1009 a->parent = ((v >> a->shift) >> 2) & 7; in alchemy_clk_setup_imux()
1017 c = clk_register(NULL, &a->hw); in alchemy_clk_setup_imux()
1018 if (IS_ERR(c)) in alchemy_clk_setup_imux()
1021 clk_register_clkdev(c, id.name, NULL); in alchemy_clk_setup_imux()
1043 struct clk *c; in alchemy_clk_init() local
1046 c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL, in alchemy_clk_init()
1048 ERRCK(c) in alchemy_clk_init()
1051 c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype); in alchemy_clk_init()
1052 ERRCK(c) in alchemy_clk_init()
1056 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK, in alchemy_clk_init()
1058 ERRCK(c) in alchemy_clk_init()
1061 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, in alchemy_clk_init()
1064 ERRCK(c) in alchemy_clk_init()
1067 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */ in alchemy_clk_init()
1068 c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK); in alchemy_clk_init()
1069 ERRCK(c) in alchemy_clk_init()
1072 c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK); in alchemy_clk_init()
1073 ERRCK(c) in alchemy_clk_init()
1076 c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype); in alchemy_clk_init()
1077 ERRCK(c) in alchemy_clk_init()
1080 c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype); in alchemy_clk_init()
1081 ERRCK(c) in alchemy_clk_init()