Lines Matching +full:pll +full:- +full:1
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
19 #include <linux/clk-provider.h>
22 #include <dt-bindings/clock/ath79-clk.h>
26 #include <asm/mach-ath79/ath79.h>
27 #include <asm/mach-ath79/ar71xx_regs.h>
63 u32 pll; in ar71xx_clocks_init() local
69 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
71 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
74 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
77 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
80 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
106 u32 pll; in ar724x_clk_init() local
109 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clk_init()
111 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); in ar724x_clk_init()
112 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; in ar724x_clk_init()
114 ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; in ar724x_clk_init()
115 ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; in ar724x_clk_init()
152 ref_div = 1; in ar9330_clk_init()
153 ninit_mul = 1; in ar9330_clk_init()
154 out_div = 1; in ar9330_clk_init()
156 cpu_div = 1; in ar9330_clk_init()
157 ddr_div = 1; in ar9330_clk_init()
158 ahb_div = 1; in ar9330_clk_init()
175 t = 1; in ar9330_clk_init()
177 out_div = (1 << t); in ar9330_clk_init()
180 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1; in ar9330_clk_init()
183 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1; in ar9330_clk_init()
186 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1; in ar9330_clk_init()
238 ret /= (1 << out_div); in ar934x_get_pll_freq()
248 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_clocks_init() local
261 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_clocks_init()
262 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { in ar934x_clocks_init()
263 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & in ar934x_clocks_init()
265 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init()
266 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & in ar934x_clocks_init()
268 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; in ar934x_clocks_init()
269 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & in ar934x_clocks_init()
271 frac = 1 << 18; in ar934x_clocks_init()
273 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
274 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in ar934x_clocks_init()
276 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_clocks_init()
278 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & in ar934x_clocks_init()
280 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in ar934x_clocks_init()
282 frac = 1 << 6; in ar934x_clocks_init()
288 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_clocks_init()
289 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { in ar934x_clocks_init()
290 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & in ar934x_clocks_init()
292 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); in ar934x_clocks_init()
293 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & in ar934x_clocks_init()
295 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; in ar934x_clocks_init()
296 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & in ar934x_clocks_init()
298 frac = 1 << 18; in ar934x_clocks_init()
300 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
301 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in ar934x_clocks_init()
303 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_clocks_init()
305 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & in ar934x_clocks_init()
307 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & in ar934x_clocks_init()
309 frac = 1 << 10; in ar934x_clocks_init()
323 cpu_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
325 cpu_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
333 ddr_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
335 ddr_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
343 ahb_rate = ddr_pll / (postdiv + 1); in ar934x_clocks_init()
345 ahb_rate = cpu_pll / (postdiv + 1); in ar934x_clocks_init()
364 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca953x_clocks_init() local
374 pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG); in qca953x_clocks_init()
375 out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in qca953x_clocks_init()
377 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in qca953x_clocks_init()
379 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & in qca953x_clocks_init()
381 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in qca953x_clocks_init()
386 cpu_pll /= (1 << out_div); in qca953x_clocks_init()
388 pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG); in qca953x_clocks_init()
389 out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in qca953x_clocks_init()
391 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in qca953x_clocks_init()
393 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & in qca953x_clocks_init()
395 frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) & in qca953x_clocks_init()
400 ddr_pll /= (1 << out_div); in qca953x_clocks_init()
410 cpu_rate = cpu_pll / (postdiv + 1); in qca953x_clocks_init()
412 cpu_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
420 ddr_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
422 ddr_rate = cpu_pll / (postdiv + 1); in qca953x_clocks_init()
430 ahb_rate = ddr_pll / (postdiv + 1); in qca953x_clocks_init()
432 ahb_rate = cpu_pll / (postdiv + 1); in qca953x_clocks_init()
449 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca955x_clocks_init() local
459 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG); in qca955x_clocks_init()
460 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in qca955x_clocks_init()
462 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in qca955x_clocks_init()
464 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & in qca955x_clocks_init()
466 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in qca955x_clocks_init()
470 cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); in qca955x_clocks_init()
471 cpu_pll /= (1 << out_div); in qca955x_clocks_init()
473 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG); in qca955x_clocks_init()
474 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in qca955x_clocks_init()
476 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in qca955x_clocks_init()
478 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & in qca955x_clocks_init()
480 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) & in qca955x_clocks_init()
484 ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); in qca955x_clocks_init()
485 ddr_pll /= (1 << out_div); in qca955x_clocks_init()
495 cpu_rate = ddr_pll / (postdiv + 1); in qca955x_clocks_init()
497 cpu_rate = cpu_pll / (postdiv + 1); in qca955x_clocks_init()
505 ddr_rate = cpu_pll / (postdiv + 1); in qca955x_clocks_init()
507 ddr_rate = ddr_pll / (postdiv + 1); in qca955x_clocks_init()
515 ahb_rate = ddr_pll / (postdiv + 1); in qca955x_clocks_init()
517 ahb_rate = cpu_pll / (postdiv + 1); in qca955x_clocks_init()
534 u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; in qca956x_clocks_init() local
554 pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG); in qca956x_clocks_init()
555 out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in qca956x_clocks_init()
557 ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in qca956x_clocks_init()
560 pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG); in qca956x_clocks_init()
561 nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & in qca956x_clocks_init()
563 hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) & in qca956x_clocks_init()
565 lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) & in qca956x_clocks_init()
571 cpu_pll /= (1 << out_div); in qca956x_clocks_init()
573 pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG); in qca956x_clocks_init()
574 out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in qca956x_clocks_init()
576 ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in qca956x_clocks_init()
578 pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG); in qca956x_clocks_init()
579 nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & in qca956x_clocks_init()
581 hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) & in qca956x_clocks_init()
583 lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) & in qca956x_clocks_init()
589 ddr_pll /= (1 << out_div); in qca956x_clocks_init()
599 cpu_rate = ddr_pll / (postdiv + 1); in qca956x_clocks_init()
601 cpu_rate = cpu_pll / (postdiv + 1); in qca956x_clocks_init()
609 ddr_rate = cpu_pll / (postdiv + 1); in qca956x_clocks_init()
611 ddr_rate = ddr_pll / (postdiv + 1); in qca956x_clocks_init()
619 ahb_rate = ddr_pll / (postdiv + 1); in qca956x_clocks_init()
621 ahb_rate = cpu_pll / (postdiv + 1); in qca956x_clocks_init()
674 CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
675 CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
676 CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
677 CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
692 pr_err("%pOF: can't map pll registers\n", np); in ath79_clocks_init_dt_ng()
696 if (of_device_is_compatible(np, "qca,ar9130-pll")) in ath79_clocks_init_dt_ng()
698 else if (of_device_is_compatible(np, "qca,ar9330-pll")) in ath79_clocks_init_dt_ng()
721 CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
722 CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);