Lines Matching full:barrier

19  * As compared to the completion barrier, the ordering barrier is a
25  * This potentially reduces how many cycles the barrier instruction must stall
40  * - The barrier does not guarantee the order in which instruction fetches are
45  *   stype zero always does a completion barrier that affects both loads and
52  *   act the same as stype zero completion barrier. This allows software written
53  *   for an implementation with a lighter-weight barrier to work on another
54  *   implementation which only implements the stype zero completion barrier.
56  * - A completion barrier is required, potentially in conjunction with SSNOP (in
59  *   mode changes. For example, a completion barrier is required on some
65  * stype 0 - A completion barrier that affects preceding loads and stores and
92  * - The barrier does not guarantee the order in which instruction fetches are
97  * stype 0x10 - An ordering barrier that affects preceding loads and stores and
139 # define fast_rmb()	barrier()
187 #  define __smp_rmb()	barrier()
195 #define __smp_mb()	barrier()
196 #define __smp_rmb()	barrier()
197 #define __smp_wmb()	barrier()
225 #include <asm-generic/barrier.h>