Lines Matching +full:25 +full:- +full:18
19 #include <asm/isa-rev.h>
84 #define CP0_WATCHLO $18
91 #define CP0_PERFORMANCE $25
110 #define CP0_IWATCH $18
151 #define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
152 #define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
247 #define PL_256K 18
462 #define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
463 #define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
468 #define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
500 #define CONF_EW (_ULCAST_(3) << 18)
547 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
556 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
596 #define MIPS_CONF1_TLBS_SHIFT (25)
626 #define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
630 #define MIPS_CONF3_SC (_ULCAST_(1) << 25)
644 /* bits 10:8 in FTLB-only configurations */
646 /* bits 12:8 in VTLB-FTLB only configurations */
670 #define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
679 /* Loongson-3 FTLB on/off bit */
766 #define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
770 #define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
798 #define MIPS_PWFIELD_UDI_SHIFT 18
811 #define MIPS_PWSIZE_UDW_SHIFT 18
846 #define MIPS_GCTL0_GT_SHIFT 25
856 #define MIPS_GCTL0_PT_SHIFT 18
901 #define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
902 #define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
903 #define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
1023 #define CP1_FCCR $25
1034 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
1080 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
1082 #define FPU_CSR_COND1_S 25 /* $fcc1 */
1104 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1138 #define FPU_CSR_RD 0x3 /* towards -Infinity */
1158 * microMIPS instructions can be 16-bit or 32-bit in length. This
1159 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1196 * parse_r var, r - Helper assembler macro for parsing register names.
1223 "\\var = -1\n\t"
1228 _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1230 _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1295 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1297 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1459 * physical address space running the 32-bit kernel. That's none atm :-)
1699 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1700 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1701 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1702 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1703 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1704 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1705 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1706 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1707 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1708 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1709 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1710 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1711 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1712 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1713 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1714 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1777 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1778 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1779 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1780 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1781 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1782 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1783 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1784 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1785 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1786 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1787 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1788 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1789 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1790 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1791 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1792 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1793 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1794 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1795 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1796 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1797 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1798 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1799 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1800 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
2159 #define read_gc0_watchlo0() __read_ulong_gc0_register($18, 0)
2160 #define read_gc0_watchlo1() __read_ulong_gc0_register($18, 1)
2161 #define read_gc0_watchlo2() __read_ulong_gc0_register($18, 2)
2162 #define read_gc0_watchlo3() __read_ulong_gc0_register($18, 3)
2163 #define read_gc0_watchlo4() __read_ulong_gc0_register($18, 4)
2164 #define read_gc0_watchlo5() __read_ulong_gc0_register($18, 5)
2165 #define read_gc0_watchlo6() __read_ulong_gc0_register($18, 6)
2166 #define read_gc0_watchlo7() __read_ulong_gc0_register($18, 7)
2167 #define write_gc0_watchlo0(val) __write_ulong_gc0_register($18, 0, val)
2168 #define write_gc0_watchlo1(val) __write_ulong_gc0_register($18, 1, val)
2169 #define write_gc0_watchlo2(val) __write_ulong_gc0_register($18, 2, val)
2170 #define write_gc0_watchlo3(val) __write_ulong_gc0_register($18, 3, val)
2171 #define write_gc0_watchlo4(val) __write_ulong_gc0_register($18, 4, val)
2172 #define write_gc0_watchlo5(val) __write_ulong_gc0_register($18, 5, val)
2173 #define write_gc0_watchlo6(val) __write_ulong_gc0_register($18, 6, val)
2174 #define write_gc0_watchlo7(val) __write_ulong_gc0_register($18, 7, val)
2196 #define read_gc0_perfctrl0() __read_32bit_gc0_register($25, 0)
2197 #define write_gc0_perfctrl0(val) __write_32bit_gc0_register($25, 0, val)
2198 #define read_gc0_perfcntr0() __read_32bit_gc0_register($25, 1)
2199 #define write_gc0_perfcntr0(val) __write_32bit_gc0_register($25, 1, val)
2200 #define read_gc0_perfcntr0_64() __read_64bit_gc0_register($25, 1)
2201 #define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register($25, 1, val)
2202 #define read_gc0_perfctrl1() __read_32bit_gc0_register($25, 2)
2203 #define write_gc0_perfctrl1(val) __write_32bit_gc0_register($25, 2, val)
2204 #define read_gc0_perfcntr1() __read_32bit_gc0_register($25, 3)
2205 #define write_gc0_perfcntr1(val) __write_32bit_gc0_register($25, 3, val)
2206 #define read_gc0_perfcntr1_64() __read_64bit_gc0_register($25, 3)
2207 #define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register($25, 3, val)
2208 #define read_gc0_perfctrl2() __read_32bit_gc0_register($25, 4)
2209 #define write_gc0_perfctrl2(val) __write_32bit_gc0_register($25, 4, val)
2210 #define read_gc0_perfcntr2() __read_32bit_gc0_register($25, 5)
2211 #define write_gc0_perfcntr2(val) __write_32bit_gc0_register($25, 5, val)
2212 #define read_gc0_perfcntr2_64() __read_64bit_gc0_register($25, 5)
2213 #define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register($25, 5, val)
2214 #define read_gc0_perfctrl3() __read_32bit_gc0_register($25, 6)
2215 #define write_gc0_perfctrl3(val) __write_32bit_gc0_register($25, 6, val)
2216 #define read_gc0_perfcntr3() __read_32bit_gc0_register($25, 7)
2217 #define write_gc0_perfcntr3(val) __write_32bit_gc0_register($25, 7, val)
2218 #define read_gc0_perfcntr3_64() __read_64bit_gc0_register($25, 7)
2219 #define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register($25, 7, val)