Lines Matching +full:1 +full:- +full:2
28 #include <asm/mips-r2-to-r6-emul.h>
63 mipsr2_emulation = 1; in mipsr2emu_enable()
65 pr_info("MIPS R2-to-R6 Emulator Enabled!"); in mipsr2emu_enable()
67 return 1; in mipsr2emu_enable()
72 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
83 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
84 (s32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
92 regs->regs[MIPSInst_RT(ir)] = in mipsr6_emul()
93 (s64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
101 return -SIGFPE; in mipsr6_emul()
106 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
107 regs->regs[MIPSInst_RS(ir)] | in mipsr6_emul()
108 regs->regs[MIPSInst_RT(ir)]; in mipsr6_emul()
115 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
116 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) << in mipsr6_emul()
124 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
125 (s32)(((u32)regs->regs[MIPSInst_RT(ir)]) >> in mipsr6_emul()
133 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
134 (s32)((u32)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
135 (u32)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
142 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
143 (s32)((u32)regs->regs[MIPSInst_RS(ir)] - in mipsr6_emul()
144 (u32)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
151 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
152 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) << in mipsr6_emul()
160 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
161 (s64)(((u64)regs->regs[MIPSInst_RT(ir)]) >> in mipsr6_emul()
169 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
170 (u64)regs->regs[MIPSInst_RS(ir)] + in mipsr6_emul()
171 (u64)regs->regs[MIPSInst_RT(ir)]; in mipsr6_emul()
178 regs->regs[MIPSInst_RD(ir)] = in mipsr6_emul()
179 (s64)((u64)regs->regs[MIPSInst_RS(ir)] - in mipsr6_emul()
180 (u64)regs->regs[MIPSInst_RT(ir)]); in mipsr6_emul()
193 * movf_func - Emulate a MOVF instruction
204 csr = current->thread.fpu.fcr31; in movf_func()
205 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in movf_func()
208 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movf_func()
216 * movt_func - Emulate a MOVT instruction
227 csr = current->thread.fpu.fcr31; in movt_func()
228 cond = fpucondbit[MIPSInst_RT(ir) >> 2]; in movt_func()
231 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movt_func()
239 * jr_func - Emulate a JR instruction.
257 nepc = regs->cp0_epc; in jr_func()
259 regs->cp0_epc -= 4; in jr_func()
260 epc = regs->cp0_epc; in jr_func()
268 cepc = regs->cp0_epc; in jr_func()
280 * Negative err means FPU instruction in BD-slot, in jr_func()
281 * Zero err means 'BD-slot emulation done' in jr_func()
286 regs->cp0_epc = nepc; in jr_func()
298 * movz_func - Emulate a MOVZ instruction
306 if (((regs->regs[MIPSInst_RT(ir)]) == 0) && MIPSInst_RD(ir)) in movz_func()
307 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movz_func()
314 * movn_func - Emulate a MOVZ instruction
322 if (((regs->regs[MIPSInst_RT(ir)]) != 0) && MIPSInst_RD(ir)) in movn_func()
323 regs->regs[MIPSInst_RD(ir)] = regs->regs[MIPSInst_RS(ir)]; in movn_func()
330 * mfhi_func - Emulate a MFHI instruction
339 regs->regs[MIPSInst_RD(ir)] = regs->hi; in mfhi_func()
347 * mthi_func - Emulate a MTHI instruction
355 regs->hi = regs->regs[MIPSInst_RS(ir)]; in mthi_func()
363 * mflo_func - Emulate a MFLO instruction
372 regs->regs[MIPSInst_RD(ir)] = regs->lo; in mflo_func()
380 * mtlo_func - Emulate a MTLO instruction
388 regs->lo = regs->regs[MIPSInst_RS(ir)]; in mtlo_func()
396 * mult_func - Emulate a MULT instruction
407 rt = regs->regs[MIPSInst_RT(ir)]; in mult_func()
408 rs = regs->regs[MIPSInst_RS(ir)]; in mult_func()
412 regs->lo = (s64)rs; in mult_func()
415 regs->hi = res; in mult_func()
423 * multu_func - Emulate a MULTU instruction
434 rt = regs->regs[MIPSInst_RT(ir)]; in multu_func()
435 rs = regs->regs[MIPSInst_RS(ir)]; in multu_func()
438 regs->lo = (s64)(s32)rt; in multu_func()
439 regs->hi = (s64)(s32)(res >> 32); in multu_func()
447 * div_func - Emulate a DIV instruction
457 rt = regs->regs[MIPSInst_RT(ir)]; in div_func()
458 rs = regs->regs[MIPSInst_RS(ir)]; in div_func()
460 regs->lo = (s64)(rs / rt); in div_func()
461 regs->hi = (s64)(rs % rt); in div_func()
469 * divu_func - Emulate a DIVU instruction
479 rt = regs->regs[MIPSInst_RT(ir)]; in divu_func()
480 rs = regs->regs[MIPSInst_RS(ir)]; in divu_func()
482 regs->lo = (s64)(rs / rt); in divu_func()
483 regs->hi = (s64)(rs % rt); in divu_func()
491 * dmult_func - Emulate a DMULT instruction
495 * Returns 0 on success or SIGILL for 32-bit kernels.
505 rt = regs->regs[MIPSInst_RT(ir)]; in dmult_func()
506 rs = regs->regs[MIPSInst_RS(ir)]; in dmult_func()
509 regs->lo = res; in dmult_func()
511 "dmuh %0, %1, %2\t\n" in dmult_func()
515 regs->hi = res; in dmult_func()
523 * dmultu_func - Emulate a DMULTU instruction
527 * Returns 0 on success or SIGILL for 32-bit kernels.
537 rt = regs->regs[MIPSInst_RT(ir)]; in dmultu_func()
538 rs = regs->regs[MIPSInst_RS(ir)]; in dmultu_func()
541 regs->lo = res; in dmultu_func()
543 "dmuhu %0, %1, %2\t\n" in dmultu_func()
547 regs->hi = res; in dmultu_func()
555 * ddiv_func - Emulate a DDIV instruction
559 * Returns 0 on success or SIGILL for 32-bit kernels.
568 rt = regs->regs[MIPSInst_RT(ir)]; in ddiv_func()
569 rs = regs->regs[MIPSInst_RS(ir)]; in ddiv_func()
571 regs->lo = rs / rt; in ddiv_func()
572 regs->hi = rs % rt; in ddiv_func()
580 * ddivu_func - Emulate a DDIVU instruction
584 * Returns 0 on success or SIGILL for 32-bit kernels.
593 rt = regs->regs[MIPSInst_RT(ir)]; in ddivu_func()
594 rs = regs->regs[MIPSInst_RS(ir)]; in ddivu_func()
596 regs->lo = rs / rt; in ddivu_func()
597 regs->hi = rs % rt; in ddivu_func()
627 * madd_func - Emulate a MADD instruction
638 rt = regs->regs[MIPSInst_RT(ir)]; in madd_func()
639 rs = regs->regs[MIPSInst_RS(ir)]; in madd_func()
641 rt = regs->hi; in madd_func()
642 rs = regs->lo; in madd_func()
646 regs->lo = (s64)rt; in madd_func()
648 regs->hi = (s64)rs; in madd_func()
656 * maddu_func - Emulate a MADDU instruction
667 rt = regs->regs[MIPSInst_RT(ir)]; in maddu_func()
668 rs = regs->regs[MIPSInst_RS(ir)]; in maddu_func()
670 rt = regs->hi; in maddu_func()
671 rs = regs->lo; in maddu_func()
675 regs->lo = (s64)(s32)rt; in maddu_func()
677 regs->hi = (s64)(s32)rs; in maddu_func()
685 * msub_func - Emulate a MSUB instruction
696 rt = regs->regs[MIPSInst_RT(ir)]; in msub_func()
697 rs = regs->regs[MIPSInst_RS(ir)]; in msub_func()
699 rt = regs->hi; in msub_func()
700 rs = regs->lo; in msub_func()
701 res = ((((s64)rt) << 32) | (u32)rs) - res; in msub_func()
704 regs->lo = (s64)rt; in msub_func()
706 regs->hi = (s64)rs; in msub_func()
714 * msubu_func - Emulate a MSUBU instruction
725 rt = regs->regs[MIPSInst_RT(ir)]; in msubu_func()
726 rs = regs->regs[MIPSInst_RS(ir)]; in msubu_func()
728 rt = regs->hi; in msubu_func()
729 rs = regs->lo; in msubu_func()
730 res = ((((s64)rt) << 32) | (u32)rs) - res; in msubu_func()
733 regs->lo = (s64)(s32)rt; in msubu_func()
735 regs->hi = (s64)(s32)rs; in msubu_func()
743 * mul_func - Emulate a MUL instruction
756 rt = regs->regs[MIPSInst_RT(ir)]; in mul_func()
757 rs = regs->regs[MIPSInst_RS(ir)]; in mul_func()
761 regs->regs[MIPSInst_RD(ir)] = (s64)rs; in mul_func()
769 * clz_func - Emulate a CLZ instruction
783 rs = regs->regs[MIPSInst_RS(ir)]; in clz_func()
784 __asm__ __volatile__("clz %0, %1" : "=r"(res) : "r"(rs)); in clz_func()
785 regs->regs[MIPSInst_RD(ir)] = res; in clz_func()
793 * clo_func - Emulate a CLO instruction
808 rs = regs->regs[MIPSInst_RS(ir)]; in clo_func()
809 __asm__ __volatile__("clo %0, %1" : "=r"(res) : "r"(rs)); in clo_func()
810 regs->regs[MIPSInst_RD(ir)] = res; in clo_func()
818 * dclz_func - Emulate a DCLZ instruction
835 rs = regs->regs[MIPSInst_RS(ir)]; in dclz_func()
836 __asm__ __volatile__("dclz %0, %1" : "=r"(res) : "r"(rs)); in dclz_func()
837 regs->regs[MIPSInst_RD(ir)] = res; in dclz_func()
845 * dclo_func - Emulate a DCLO instruction
862 rs = regs->regs[MIPSInst_RS(ir)]; in dclo_func()
863 __asm__ __volatile__("dclo %0, %1" : "=r"(res) : "r"(rs)); in dclo_func()
864 regs->regs[MIPSInst_RD(ir)] = res; in dclo_func()
891 for (p = table; p->func; p++) { in mipsr2_find_op_func()
892 if ((inst & p->mask) == p->code) { in mipsr2_find_op_func()
893 err = (p->func)(regs, inst); in mipsr2_find_op_func()
917 r31 = regs->regs[31]; in mipsr2_decoder()
918 epc = regs->cp0_epc; in mipsr2_decoder()
932 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
944 if ((long)regs->regs[rs] >= MIPSInst_SIMM(inst)) in mipsr2_decoder()
951 if (regs->regs[rs] >= MIPSInst_UIMM(inst)) in mipsr2_decoder()
958 if ((long)regs->regs[rs] < MIPSInst_SIMM(inst)) in mipsr2_decoder()
965 if (regs->regs[rs] < MIPSInst_UIMM(inst)) in mipsr2_decoder()
972 if (regs->regs[rs] == MIPSInst_SIMM(inst)) in mipsr2_decoder()
979 if (regs->regs[rs] != MIPSInst_SIMM(inst)) in mipsr2_decoder()
993 regs->regs[31] = r31; in mipsr2_decoder()
994 regs->cp0_epc = epc; in mipsr2_decoder()
1000 cpc = regs->cp0_epc; in mipsr2_decoder()
1031 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1050 regs->regs[31] = r31; in mipsr2_decoder()
1051 regs->cp0_epc = epc; in mipsr2_decoder()
1055 cpc = regs->cp0_epc; in mipsr2_decoder()
1080 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1094 regs->regs[31] = r31; in mipsr2_decoder()
1095 regs->cp0_epc = epc; in mipsr2_decoder()
1119 regs->regs[31] = r31; in mipsr2_decoder()
1120 regs->cp0_epc = epc; in mipsr2_decoder()
1126 cpc = regs->cp0_epc; in mipsr2_decoder()
1157 regs->cp0_cause |= CAUSEF_BD; in mipsr2_decoder()
1175 regs->regs[31] = r31; in mipsr2_decoder()
1176 regs->cp0_epc = epc; in mipsr2_decoder()
1183 lose_fpu(1); /* Save FPU state for the emulator. */ in mipsr2_decoder()
1185 err = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, in mipsr2_decoder()
1192 *fcr31 = res = mask_fcr31_x(current->thread.fpu.fcr31); in mipsr2_decoder()
1193 current->thread.fpu.fcr31 &= ~res; in mipsr2_decoder()
1196 * this is a tricky issue - lose_fpu() uses LL/SC atomics in mipsr2_decoder()
1200 * more often than LL-FPU-SC and I prefer loop here until in mipsr2_decoder()
1203 own_fpu(1); /* Restore FPU state. */ in mipsr2_decoder()
1206 current->thread.cp0_baduaddr = (unsigned long)fault_addr; in mipsr2_decoder()
1213 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1214 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1216 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1224 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1225 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1226 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1227 " beq $0, %1, 9f\n" in mipsr2_decoder()
1228 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1229 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1230 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1231 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1232 " beq $0, %1, 9f\n" in mipsr2_decoder()
1233 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1234 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1235 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1236 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1237 " beq $0, %1, 9f\n" in mipsr2_decoder()
1238 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1239 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1240 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1242 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1243 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1244 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1245 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1246 " beq $0, %1, 9f\n" in mipsr2_decoder()
1247 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1248 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1249 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1250 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1251 " beq $0, %1, 9f\n" in mipsr2_decoder()
1252 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1253 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1254 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1255 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1256 " beq $0, %1, 9f\n" in mipsr2_decoder()
1257 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1258 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1268 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1269 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1279 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1286 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1287 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1289 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1297 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1298 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1299 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1300 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1301 " beq $0, %1, 9f\n" in mipsr2_decoder()
1302 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1303 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1304 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1305 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1306 " beq $0, %1, 9f\n" in mipsr2_decoder()
1307 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1308 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1309 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1310 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1311 " beq $0, %1, 9f\n" in mipsr2_decoder()
1312 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1313 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1316 "1:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1317 INS "%0, %1, 0, 8\n" in mipsr2_decoder()
1318 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1319 " beq $0, %1, 9f\n" in mipsr2_decoder()
1320 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1321 "2:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1322 INS "%0, %1, 8, 8\n" in mipsr2_decoder()
1323 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1324 " beq $0, %1, 9f\n" in mipsr2_decoder()
1325 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1326 "3:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1327 INS "%0, %1, 16, 8\n" in mipsr2_decoder()
1328 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1329 " beq $0, %1, 9f\n" in mipsr2_decoder()
1330 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1331 "4:" LB "%1, 0(%2)\n" in mipsr2_decoder()
1332 INS "%0, %1, 24, 8\n" in mipsr2_decoder()
1343 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1344 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1353 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1360 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1361 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1363 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1371 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1372 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1373 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1374 " beq $0, %1, 9f\n" in mipsr2_decoder()
1375 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1376 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1377 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1378 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1379 " beq $0, %1, 9f\n" in mipsr2_decoder()
1380 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1381 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1382 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1383 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1384 " beq $0, %1, 9f\n" in mipsr2_decoder()
1385 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1386 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1387 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1389 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1390 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1391 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1392 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1393 " beq $0, %1, 9f\n" in mipsr2_decoder()
1394 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1395 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1396 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1397 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1398 " beq $0, %1, 9f\n" in mipsr2_decoder()
1399 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1400 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1401 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1402 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1403 " beq $0, %1, 9f\n" in mipsr2_decoder()
1404 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1405 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1414 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1415 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1430 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1431 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1433 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1441 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1442 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1443 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1444 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1445 " beq $0, %1, 9f\n" in mipsr2_decoder()
1446 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1447 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1448 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1449 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1450 " beq $0, %1, 9f\n" in mipsr2_decoder()
1451 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1452 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1453 ADDIU "%2, %2, 1\n" in mipsr2_decoder()
1454 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1455 " beq $0, %1, 9f\n" in mipsr2_decoder()
1456 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1457 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1459 EXT "%1, %0, 0, 8\n" in mipsr2_decoder()
1460 "1:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1461 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1462 " beq $0, %1, 9f\n" in mipsr2_decoder()
1463 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1464 EXT "%1, %0, 8, 8\n" in mipsr2_decoder()
1465 "2:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1466 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1467 " beq $0, %1, 9f\n" in mipsr2_decoder()
1468 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1469 EXT "%1, %0, 16, 8\n" in mipsr2_decoder()
1470 "3:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1471 " andi %1, %2, 0x3\n" in mipsr2_decoder()
1472 " beq $0, %1, 9f\n" in mipsr2_decoder()
1473 ADDIU "%2, %2, -1\n" in mipsr2_decoder()
1474 EXT "%1, %0, 24, 8\n" in mipsr2_decoder()
1475 "4:" SB "%1, 0(%2)\n" in mipsr2_decoder()
1484 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1485 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1505 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1506 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1508 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1516 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1517 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1518 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1519 " beq $0, %1, 9f\n" in mipsr2_decoder()
1520 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1521 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1522 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1523 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1524 " beq $0, %1, 9f\n" in mipsr2_decoder()
1525 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1526 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1527 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1528 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1529 " beq $0, %1, 9f\n" in mipsr2_decoder()
1530 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1531 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1532 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1533 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1534 " beq $0, %1, 9f\n" in mipsr2_decoder()
1535 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1536 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1537 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1538 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1539 " beq $0, %1, 9f\n" in mipsr2_decoder()
1540 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1541 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1542 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1543 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1544 " beq $0, %1, 9f\n" in mipsr2_decoder()
1545 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1546 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1547 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1548 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1549 " beq $0, %1, 9f\n" in mipsr2_decoder()
1550 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1551 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1552 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1554 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1555 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1556 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1557 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1558 " beq $0, %1, 9f\n" in mipsr2_decoder()
1559 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1560 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1561 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1562 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1563 " beq $0, %1, 9f\n" in mipsr2_decoder()
1564 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1565 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1566 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1567 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1568 " beq $0, %1, 9f\n" in mipsr2_decoder()
1569 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1570 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1571 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1572 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1573 " beq $0, %1, 9f\n" in mipsr2_decoder()
1574 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1575 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1576 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1577 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1578 " beq $0, %1, 9f\n" in mipsr2_decoder()
1579 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1580 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1581 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1582 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1583 " beq $0, %1, 9f\n" in mipsr2_decoder()
1584 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1585 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1586 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1587 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1588 " beq $0, %1, 9f\n" in mipsr2_decoder()
1589 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1590 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1599 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1600 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1613 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1624 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1625 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1627 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1635 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1636 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1637 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1638 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1639 " beq $0, %1, 9f\n" in mipsr2_decoder()
1640 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1641 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1642 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1643 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1644 " beq $0, %1, 9f\n" in mipsr2_decoder()
1645 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1646 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1647 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1648 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1649 " beq $0, %1, 9f\n" in mipsr2_decoder()
1650 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1651 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1652 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1653 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1654 " beq $0, %1, 9f\n" in mipsr2_decoder()
1655 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1656 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1657 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1658 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1659 " beq $0, %1, 9f\n" in mipsr2_decoder()
1660 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1661 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1662 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1663 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1664 " beq $0, %1, 9f\n" in mipsr2_decoder()
1665 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1666 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1667 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1668 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1669 " beq $0, %1, 9f\n" in mipsr2_decoder()
1670 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1671 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1673 "1: lb %1, 0(%2)\n" in mipsr2_decoder()
1674 " dins %0, %1, 0, 8\n" in mipsr2_decoder()
1675 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1676 " beq $0, %1, 9f\n" in mipsr2_decoder()
1677 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1678 "2: lb %1, 0(%2)\n" in mipsr2_decoder()
1679 " dins %0, %1, 8, 8\n" in mipsr2_decoder()
1680 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1681 " beq $0, %1, 9f\n" in mipsr2_decoder()
1682 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1683 "3: lb %1, 0(%2)\n" in mipsr2_decoder()
1684 " dins %0, %1, 16, 8\n" in mipsr2_decoder()
1685 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1686 " beq $0, %1, 9f\n" in mipsr2_decoder()
1687 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1688 "4: lb %1, 0(%2)\n" in mipsr2_decoder()
1689 " dins %0, %1, 24, 8\n" in mipsr2_decoder()
1690 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1691 " beq $0, %1, 9f\n" in mipsr2_decoder()
1692 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1693 "5: lb %1, 0(%2)\n" in mipsr2_decoder()
1694 " dinsu %0, %1, 32, 8\n" in mipsr2_decoder()
1695 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1696 " beq $0, %1, 9f\n" in mipsr2_decoder()
1697 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1698 "6: lb %1, 0(%2)\n" in mipsr2_decoder()
1699 " dinsu %0, %1, 40, 8\n" in mipsr2_decoder()
1700 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1701 " beq $0, %1, 9f\n" in mipsr2_decoder()
1702 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1703 "7: lb %1, 0(%2)\n" in mipsr2_decoder()
1704 " dinsu %0, %1, 48, 8\n" in mipsr2_decoder()
1705 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1706 " beq $0, %1, 9f\n" in mipsr2_decoder()
1707 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1708 "0: lb %1, 0(%2)\n" in mipsr2_decoder()
1709 " dinsu %0, %1, 56, 8\n" in mipsr2_decoder()
1718 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1719 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1732 regs->regs[MIPSInst_RT(inst)] = rt; in mipsr2_decoder()
1743 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1744 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1746 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1754 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1755 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1756 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1757 " beq $0, %1, 9f\n" in mipsr2_decoder()
1758 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1759 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1760 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1761 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1762 " beq $0, %1, 9f\n" in mipsr2_decoder()
1763 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1764 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1765 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1766 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1767 " beq $0, %1, 9f\n" in mipsr2_decoder()
1768 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1769 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1770 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1771 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1772 " beq $0, %1, 9f\n" in mipsr2_decoder()
1773 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1774 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1775 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1776 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1777 " beq $0, %1, 9f\n" in mipsr2_decoder()
1778 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1779 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1780 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1781 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1782 " beq $0, %1, 9f\n" in mipsr2_decoder()
1783 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1784 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1785 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1786 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1787 " beq $0, %1, 9f\n" in mipsr2_decoder()
1788 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1789 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1790 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1792 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1793 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1794 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1795 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1796 " beq $0, %1, 9f\n" in mipsr2_decoder()
1797 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1798 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1799 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1800 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1801 " beq $0, %1, 9f\n" in mipsr2_decoder()
1802 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1803 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1804 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1805 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1806 " beq $0, %1, 9f\n" in mipsr2_decoder()
1807 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1808 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1809 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1810 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1811 " beq $0, %1, 9f\n" in mipsr2_decoder()
1812 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1813 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1814 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1815 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1816 " beq $0, %1, 9f\n" in mipsr2_decoder()
1817 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1818 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1819 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1820 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1821 " beq $0, %1, 9f\n" in mipsr2_decoder()
1822 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1823 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1824 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1825 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1826 " beq $0, %1, 9f\n" in mipsr2_decoder()
1827 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1828 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1837 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1838 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1861 rt = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
1862 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1864 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1872 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1873 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1874 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1875 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1876 " beq $0, %1, 9f\n" in mipsr2_decoder()
1877 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1878 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1879 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1880 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1881 " beq $0, %1, 9f\n" in mipsr2_decoder()
1882 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1883 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1884 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1885 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1886 " beq $0, %1, 9f\n" in mipsr2_decoder()
1887 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1888 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1889 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1890 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1891 " beq $0, %1, 9f\n" in mipsr2_decoder()
1892 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1893 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1894 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1895 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1896 " beq $0, %1, 9f\n" in mipsr2_decoder()
1897 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1898 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1899 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1900 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1901 " beq $0, %1, 9f\n" in mipsr2_decoder()
1902 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1903 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1904 " daddiu %2, %2, 1\n" in mipsr2_decoder()
1905 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1906 " beq $0, %1, 9f\n" in mipsr2_decoder()
1907 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1908 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1910 " dext %1, %0, 0, 8\n" in mipsr2_decoder()
1911 "1: sb %1, 0(%2)\n" in mipsr2_decoder()
1912 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1913 " beq $0, %1, 9f\n" in mipsr2_decoder()
1914 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1915 " dext %1, %0, 8, 8\n" in mipsr2_decoder()
1916 "2: sb %1, 0(%2)\n" in mipsr2_decoder()
1917 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1918 " beq $0, %1, 9f\n" in mipsr2_decoder()
1919 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1920 " dext %1, %0, 16, 8\n" in mipsr2_decoder()
1921 "3: sb %1, 0(%2)\n" in mipsr2_decoder()
1922 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1923 " beq $0, %1, 9f\n" in mipsr2_decoder()
1924 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1925 " dext %1, %0, 24, 8\n" in mipsr2_decoder()
1926 "4: sb %1, 0(%2)\n" in mipsr2_decoder()
1927 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1928 " beq $0, %1, 9f\n" in mipsr2_decoder()
1929 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1930 " dextu %1, %0, 32, 8\n" in mipsr2_decoder()
1931 "5: sb %1, 0(%2)\n" in mipsr2_decoder()
1932 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1933 " beq $0, %1, 9f\n" in mipsr2_decoder()
1934 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1935 " dextu %1, %0, 40, 8\n" in mipsr2_decoder()
1936 "6: sb %1, 0(%2)\n" in mipsr2_decoder()
1937 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1938 " beq $0, %1, 9f\n" in mipsr2_decoder()
1939 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1940 " dextu %1, %0, 48, 8\n" in mipsr2_decoder()
1941 "7: sb %1, 0(%2)\n" in mipsr2_decoder()
1942 " andi %1, %2, 0x7\n" in mipsr2_decoder()
1943 " beq $0, %1, 9f\n" in mipsr2_decoder()
1944 " daddiu %2, %2, -1\n" in mipsr2_decoder()
1945 " dextu %1, %0, 56, 8\n" in mipsr2_decoder()
1946 "0: sb %1, 0(%2)\n" in mipsr2_decoder()
1955 STR(PTR) " 1b,8b\n" in mipsr2_decoder()
1956 STR(PTR) " 2b,8b\n" in mipsr2_decoder()
1974 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
1976 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
1981 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2007 "1:\n" in mipsr2_decoder()
2008 "ll %0, 0(%2)\n" in mipsr2_decoder()
2009 "2:\n" in mipsr2_decoder()
2013 "li %1, %3\n" in mipsr2_decoder()
2014 "j 2b\n" in mipsr2_decoder()
2017 STR(PTR) " 1b,3b\n" in mipsr2_decoder()
2024 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2030 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2032 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2037 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2062 res = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
2065 "1:\n" in mipsr2_decoder()
2066 "sc %0, 0(%2)\n" in mipsr2_decoder()
2067 "2:\n" in mipsr2_decoder()
2071 "li %1, %3\n" in mipsr2_decoder()
2072 "j 2b\n" in mipsr2_decoder()
2075 STR(PTR) " 1b,3b\n" in mipsr2_decoder()
2081 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2093 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2095 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2100 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2126 "1:\n" in mipsr2_decoder()
2127 "lld %0, 0(%2)\n" in mipsr2_decoder()
2128 "2:\n" in mipsr2_decoder()
2132 "li %1, %3\n" in mipsr2_decoder()
2133 "j 2b\n" in mipsr2_decoder()
2136 STR(PTR) " 1b,3b\n" in mipsr2_decoder()
2142 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2154 vaddr = regs->regs[MIPSInst_RS(inst)] + MIPSInst_SIMM(inst); in mipsr2_decoder()
2156 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2161 current->thread.cp0_baduaddr = vaddr; in mipsr2_decoder()
2186 res = regs->regs[MIPSInst_RT(inst)]; in mipsr2_decoder()
2189 "1:\n" in mipsr2_decoder()
2190 "scd %0, 0(%2)\n" in mipsr2_decoder()
2191 "2:\n" in mipsr2_decoder()
2195 "li %1, %3\n" in mipsr2_decoder()
2196 "j 2b\n" in mipsr2_decoder()
2199 STR(PTR) " 1b,3b\n" in mipsr2_decoder()
2205 regs->regs[MIPSInst_RT(inst)] = res; in mipsr2_decoder()
2222 regs->cp0_cause &= ~CAUSEF_BD; in mipsr2_decoder()
2223 err = get_user(inst, (u32 __user *)regs->cp0_epc); in mipsr2_decoder()
2232 regs->regs[31] = r31; in mipsr2_decoder()
2233 regs->cp0_epc = epc; in mipsr2_decoder()
2248 seq_printf(s, "Instruction\tTotal\tBDslot\n------------------------------\n"); in mipsr2_stats_show()
2358 return single_open(file, mipsr2_stats_show, inode->i_private); in mipsr2_stats_open()
2363 return single_open(file, mipsr2_stats_clear_show, inode->i_private); in mipsr2_stats_clear_open()
2386 return -ENODEV; in mipsr2_init_debugfs()
2392 return -ENOMEM; in mipsr2_init_debugfs()
2398 return -ENOMEM; in mipsr2_init_debugfs()