Lines Matching +full:sw +full:- +full:exception

15 #include <asm/asm-offsets.h>
326  * The exception handler for loads requires that:
327  *  1- AT contain the address of the byte just past the end of the source
329  *  2- src_entry <= src < AT, and
330  *  3- (dst - src) == (dst_entry - src_entry),
338  * The exception handlers for stores stores -EFAULT to errptr and return.
351  * Wrapper to add an entry in the exception table
352  * in case the insn causes a memory exception.
358  * handler : Exception handler
376 			/* EVA without exception */		\
385 #define LOADK	ld /* No exception */
405 #define LOADK	lw /* No exception */
413 #define STORE(reg, addr, handler)	EXC(sw, ST_INSN, reg, addr, handler)
442 #define REST(unit)  (FIRST(unit)+NBYTES-1)
444 #define ADDRMASK (NBYTES-1)
489 	 * use delay slot for fall-through
539 	 and	rem, len, (NBYTES-1)	# rem = len % NBYTES
582 	 * because can't assume read-access to dst.  Instead, use
586 	 * wide-issue mips processors because the code has fewer branches and
587 	 * more instruction-level parallelism.
597 	STREST(t0, -1(t1), .Ls_exc\@)
633 	 and	rem, len, (4*NBYTES-1)	 # rem = len % 4*NBYTES
669 	 and	rem, len, NBYTES-1  # rem = len % NBYTES
693 #define SHIFT_START 8*(NBYTES-1)
694 #define SHIFT_INC -8
716 	LOADBU(t0, NBYTES-2(src), .Ll_exc_copy\@)
718 	STOREB(t0, NBYTES-2(dst), .Ls_exc\@)
765 	 * Hence, the lb below may get an exception.
775 	sb	t1, 0(dst)	# can't fault -- we're copy_from_user
792 	 * dst += (fault addr - src) to put dst at first byte to clear
816 	li	v1, -EFAULT
818 	 sw	v1, (errptr)
821 	li	v0, -1 /* invalid checksum */
822 	li	v1, -EFAULT
824 	 sw	v1, (errptr)