6  * Copyright (C) 2005-2007 Cavium Networks
20 #include <asm/cpu-features.h>
21 #include <asm/cpu-type.h>
37  * tagged cache. No flushing is needed
51  * Flush local I-cache for the specified range.
84 		mask = *mm_cpumask(vma->vm_mm);  in octeon_flush_icache_all_cores()
140 	down_read(&current->mm->mmap_sem);  in octeon_flush_cache_sigtramp()
141 	vma = find_vma(current->mm, addr);  in octeon_flush_cache_sigtramp()
143 	up_read(&current->mm->mmap_sem);  in octeon_flush_cache_sigtramp()
157 	if (vma->vm_flags & VM_EXEC)  in octeon_flush_cache_range()
172 	if (vma->vm_flags & VM_EXEC)  in octeon_flush_cache_page()
197 		c->icache.linesz = 2 << ((config1 >> 19) & 7);  in probe_octeon()
198 		c->icache.sets = 64 << ((config1 >> 22) & 7);  in probe_octeon()
199 		c->icache.ways = 1 + ((config1 >> 16) & 7);  in probe_octeon()
200 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
202 			c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
203 		c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;  in probe_octeon()
204 		c->dcache.linesz = 128;  in probe_octeon()
206 			c->dcache.sets = 2; /* CN5XXX has two Dcache sets */  in probe_octeon()
208 			c->dcache.sets = 1; /* CN3XXX has one Dcache set */  in probe_octeon()
209 		c->dcache.ways = 64;  in probe_octeon()
211 			c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
212 		c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;  in probe_octeon()
213 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
217 		c->icache.linesz = 2 << ((config1 >> 19) & 7);  in probe_octeon()
218 		c->icache.sets = 8;  in probe_octeon()
219 		c->icache.ways = 37;  in probe_octeon()
220 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
221 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
223 		c->dcache.linesz = 128;  in probe_octeon()
224 		c->dcache.ways = 32;  in probe_octeon()
225 		c->dcache.sets = 8;  in probe_octeon()
226 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
227 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
231 		c->icache.linesz = 128;  in probe_octeon()
232 		c->icache.sets = 16;  in probe_octeon()
233 		c->icache.ways = 39;  in probe_octeon()
234 		c->icache.flags |= MIPS_CACHE_VTAG;  in probe_octeon()
235 		icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;  in probe_octeon()
237 		c->dcache.linesz = 128;  in probe_octeon()
238 		c->dcache.ways = 32;  in probe_octeon()
239 		c->dcache.sets = 8;  in probe_octeon()
240 		dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;  in probe_octeon()
241 		c->options |= MIPS_CPU_PREFETCH;  in probe_octeon()
249 	/* compute a couple of other cache variables */  in probe_octeon()
250 	c->icache.waysize = icache_size / c->icache.ways;  in probe_octeon()
251 	c->dcache.waysize = dcache_size / c->dcache.ways;  in probe_octeon()
253 	c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);  in probe_octeon()
254 	c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);  in probe_octeon()
257 		pr_notice("Primary instruction cache %ldkB, %s, %d way, "  in probe_octeon()
258 			  "%d sets, linesize %d bytes.\n",  in probe_octeon()
262 			  c->icache.ways, c->icache.sets, c->icache.linesz);  in probe_octeon()
264 		pr_notice("Primary data cache %ldkB, %d-way, %d sets, "  in probe_octeon()
266 			  dcache_size >> 10, c->dcache.ways,  in probe_octeon()
267 			  c->dcache.sets, c->dcache.linesz);  in probe_octeon()
278  * Setup the Octeon cache flush routines
285 	shm_align_mask = PAGE_SIZE - 1;  in octeon_cache_init()
309  * Handle a cache error exception
340 		pr_err("Core%lu: Cache error exception:\n", coreid);  in co_cache_error_call_notifiers()
370 	panic("Can't handle cache error: nested exception");  in cache_parity_error_octeon_non_recoverable()