1 // SPDX-License-Identifier: GPL-2.0
10 #include <asm/cpu-type.h>
18 #include <asm/mips-cps.h>
22  * MIPS32/MIPS64 L2 cache handling
26  * Writeback and invalidate the secondary cache before DMA.
34  * Invalidate the secondary cache before DMA.
39 	unsigned long almask = ~(lsize - 1);  in mips_sc_inv()
42 	cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask);  in mips_sc_inv()
48 	/* L2 cache is permanently enabled */  in mips_sc_enable()
53 	/* L2 cache is permanently enabled */  in mips_sc_disable()
113  * Check if the L2 cache controller is activated on a particular platform.
114  * MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS
116  * cache being disabled.  However there is no guarantee for this to be
144 		c->scache.linesz = 2 << tmp;  in mips_sc_is_activated()
154 	unsigned long sets, line_sz, assoc;  in mips_sc_probe_cm3()  local
159 	sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE;  in mips_sc_probe_cm3()
160 	sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE);  in mips_sc_probe_cm3()
161 	if (sets)  in mips_sc_probe_cm3()
162 		c->scache.sets = 64 << sets;  in mips_sc_probe_cm3()
167 		c->scache.linesz = 2 << line_sz;  in mips_sc_probe_cm3()
171 	c->scache.ways = assoc + 1;  in mips_sc_probe_cm3()
172 	c->scache.waysize = c->scache.sets * c->scache.linesz;  in mips_sc_probe_cm3()
173 	c->scache.waybit = __ffs(c->scache.waysize);  in mips_sc_probe_cm3()
175 	if (c->scache.linesz) {  in mips_sc_probe_cm3()
176 		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;  in mips_sc_probe_cm3()
177 		c->options |= MIPS_CPU_INCLUSIVE_CACHES;  in mips_sc_probe_cm3()
191 	c->scache.flags |= MIPS_CACHE_NOT_PRESENT;  in mips_sc_probe()
197 	if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |  in mips_sc_probe()
214 		c->scache.sets = 64 << tmp;  in mips_sc_probe()
220 		c->scache.ways = tmp + 1;  in mips_sc_probe()
225 	 * According to config2 it would be 5-ways, but that is contradicted  in mips_sc_probe()
230 		c->scache.ways = 4;  in mips_sc_probe()
232 	c->scache.waysize = c->scache.sets * c->scache.linesz;  in mips_sc_probe()
233 	c->scache.waybit = __ffs(c->scache.waysize);  in mips_sc_probe()
235 	c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;  in mips_sc_probe()