7  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
20  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
30 #include <asm/mips-cps.h>
31 #include <asm/mips-boards/generic.h>
32 #include <asm/mips-boards/bonito64.h>
33 #include <asm/mips-boards/msc01_pci.h>
42 	.start	= 0x00000000UL,
48 	.name	= "GT-64120 PCI MEM",
53 	.name	= "GT-64120 PCI I/O",
93 	resource_size_t start, end, map, start1, end1, map1, map2, map3, mask;  in mips_pcibios_init()  local
114 		/* Set up resource ranges from the controller's registers.  */  in mips_pcibios_init()
115 		start = GT_READ(GT_PCI0M0LD_OFS);  in mips_pcibios_init()
118 		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);  in mips_pcibios_init()
124 		if (end1 - start1 > end - start) {  in mips_pcibios_init()
125 			start = start1;  in mips_pcibios_init()
129 		mask = ~(start ^ end);  in mips_pcibios_init()
131 		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&  in mips_pcibios_init()
132 		       mask != ~((mask & -mask) - 1));  in mips_pcibios_init()
133 		gt64120_mem_resource.start = start;  in mips_pcibios_init()
135 		gt64120_controller.mem_offset = (start & mask) - (map & mask);  in mips_pcibios_init()
136 		/* Addresses are 36-bit, so do shifts in the destinations.  */  in mips_pcibios_init()
137 		gt64120_mem_resource.start <<= GT_PCI_DCRM_SHF;  in mips_pcibios_init()
139 		gt64120_mem_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;  in mips_pcibios_init()
142 		start = GT_READ(GT_PCI0IOLD_OFS);  in mips_pcibios_init()
145 		end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);  in mips_pcibios_init()
146 		mask = ~(start ^ end);  in mips_pcibios_init()
148 		BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&  in mips_pcibios_init()
149 		       mask != ~((mask & -mask) - 1));  in mips_pcibios_init()
150 		gt64120_io_resource.start = map & mask;  in mips_pcibios_init()
153 		/* Addresses are 36-bit, so do shifts in the destinations.  */  in mips_pcibios_init()
154 		gt64120_io_resource.start <<= GT_PCI_DCRM_SHF;  in mips_pcibios_init()
156 		gt64120_io_resource.end |= (1 << GT_PCI_DCRM_SHF) - 1;  in mips_pcibios_init()
162 		/* Set up resource ranges from the controller's registers.  */  in mips_pcibios_init()
172 		start = BONITO_PCILO0_BASE;  in mips_pcibios_init()
176 			start = BONITO_PCILO1_BASE;  in mips_pcibios_init()
181 			start = BONITO_PCILO0_BASE;  in mips_pcibios_init()
184 		bonito64_mem_resource.start = start;  in mips_pcibios_init()
185 		bonito64_mem_resource.end = start +  in mips_pcibios_init()
186 					    BONITO_PCIMAP_WINBASE(end) - 1;  in mips_pcibios_init()
187 		bonito64_controller.mem_offset = start -  in mips_pcibios_init()
197 		/* Set up resource ranges from the controller's registers.  */  in mips_pcibios_init()
198 		MSC_READ(MSC01_PCI_SC2PMBASL, start);  in mips_pcibios_init()
201 		msc_mem_resource.start = start & mask;  in mips_pcibios_init()
202 		msc_mem_resource.end = (start & mask) | ~mask;  in mips_pcibios_init()
203 		msc_controller.mem_offset = (start & mask) - (map & mask);  in mips_pcibios_init()
205 			write_gcr_reg0_base(start);  in mips_pcibios_init()
209 		MSC_READ(MSC01_PCI_SC2PIOBASL, start);  in mips_pcibios_init()
212 		msc_io_resource.start = map & mask;  in mips_pcibios_init()
217 			write_gcr_reg1_base(start);  in mips_pcibios_init()
222 		start = start & mask;  in mips_pcibios_init()
223 		end = start | ~mask;  in mips_pcibios_init()
224 		if ((start >= msc_mem_resource.start &&  in mips_pcibios_init()
225 		     start <= msc_mem_resource.end) ||  in mips_pcibios_init()
226 		    (end >= msc_mem_resource.start &&  in mips_pcibios_init()
229 			start = max(start, msc_mem_resource.start);  in mips_pcibios_init()
231 			if (start - msc_mem_resource.start >=  in mips_pcibios_init()
232 			    msc_mem_resource.end - end)  in mips_pcibios_init()
233 				msc_mem_resource.end = start - 1;  in mips_pcibios_init()
235 				msc_mem_resource.start = end + 1;  in mips_pcibios_init()
245 	if (controller->io_resource->start < 0x00001000UL)  in mips_pcibios_init()
246 		controller->io_resource->start = 0x00001000UL;  in mips_pcibios_init()
249 	ioport_resource.end = controller->io_resource->end;  in mips_pcibios_init()
251 	controller->io_map_base = mips_io_port_base;  in mips_pcibios_init()